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cpu
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cpu
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README.md
Brendan Haines
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add pipeline status to README.md
2021-08-11 06:28:00 +00:00
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RISC-V CPU
Harvard architecture
Desired features:
1- or 5-stage pipeline selectable via parameter
AXI-lite Master for both instruction and data memory
32, 64, or 128 bit word size
floating point support
multiplication
division
instruction and data caches