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cc4101c1f8
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prevent simulation from printing all writes to regfile
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2021-07-03 21:02:48 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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f0166f1954
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load (word only) appears to be working
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2020-11-14 23:13:24 -07:00 |
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4a25ca6def
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fix issue of jumping to address 0
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2020-11-14 23:04:24 -07:00 |
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32d0a2dcaa
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display more data to simplify verification
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2020-11-09 23:38:22 -07:00 |
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6e0d9c96a1
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passes quick test: beq, blt, bltu
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2020-11-09 20:01:25 -07:00 |
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82cbaba7e5
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I think this properly stalls for all implemented instructions so I don't need nops
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2020-11-07 00:47:20 -07:00 |
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1290418aa3
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properly flushes pipeline after jump
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2020-11-06 23:18:37 -07:00 |
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c98881c5d7
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passes quick test: slt, slti, sltu, sltiu
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2020-10-16 18:51:51 -06:00 |
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52a28d4e47
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passes quick test: sll, srl, sra
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2020-10-16 18:25:10 -06:00 |
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913ffb3af6
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passes quick test: slli, srli, srai
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2020-10-11 23:36:11 -06:00 |
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2c24c19a72
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passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
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2020-10-11 23:03:14 -06:00 |
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3fbd96ca27
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sub, and, or don't always work
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2020-10-03 13:49:14 -06:00 |
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2ad82e2b90
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add test assembly file
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2020-09-27 18:04:08 -06:00 |
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63ed8ace80
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initial commit. Non-working due to newly added MEM backpressure signal
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2020-09-27 16:04:16 -06:00 |
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