move axil bridge

lib/axil_wb_bridge.sv

@@ -1,6 +1,6 @@
 // TODO: improve throughput. Currently limited to 1 write every 3 cycles and read every 2 cycles (plus wb slave latency)
 
-module axi4l_wb_bridge #(
+module axil_wb_bridge #(
     parameter ADDR_WIDTH = 8,
     parameter DATA_WIDTH = 32
 )(

lib/tb/axil_wb_bridge_tb.sv

@@ -1,4 +1,10 @@
-module axi4_lite_tb();
+`include "bh_assert.sv"
+`timescale 1ns/1ps
+
+import bh_assert::bh_assert_equal;
+import bh_assert::bh_assert_stats;
+
+module axil_wb_bridge_tb();
 
 parameter ADDR_WIDTH = 8;
 parameter DATA_WIDTH = 32;
@@ -39,7 +45,7 @@ logic wb_stb_o;
 logic wb_ack_i;
 logic wb_cyc_o;
 
-axi4l_wb_bridge #(
+axil_wb_bridge #(
     .ADDR_WIDTH(ADDR_WIDTH),
     .DATA_WIDTH(DATA_WIDTH)
 ) dut(
@@ -91,6 +97,9 @@ always #5 clk <= !clk;
 
 initial begin
     
+    #10
+    bh_assert_stats();
+    $finish;
 end
 
 endmodule

lib/tb/skidbuffer_tb.sv

@@ -60,6 +60,7 @@ module skidbuffer_tb();
             end
         end
 
+        #10
         bh_assert_stats();
         $finish;
     end