From e301d2c4d24c15c8e020bd4983f941dc0af56f35 Mon Sep 17 00:00:00 2001 From: Brendan Haines Date: Thu, 1 Dec 2022 01:13:23 -0700 Subject: [PATCH] move axil bridge --- tests/common/axi4_lite.sv => lib/axil_wb_bridge.sv | 2 +- .../axi4_lite_tb.sv => lib/tb/axil_wb_bridge_tb.sv | 13 +++++++++++-- lib/tb/skidbuffer_tb.sv | 1 + 3 files changed, 13 insertions(+), 3 deletions(-) rename tests/common/axi4_lite.sv => lib/axil_wb_bridge.sv (99%) rename tests/common/axi4_lite_tb.sv => lib/tb/axil_wb_bridge_tb.sv (89%) diff --git a/tests/common/axi4_lite.sv b/lib/axil_wb_bridge.sv similarity index 99% rename from tests/common/axi4_lite.sv rename to lib/axil_wb_bridge.sv index 6835bde..a72c5b7 100644 --- a/tests/common/axi4_lite.sv +++ b/lib/axil_wb_bridge.sv @@ -1,6 +1,6 @@ // TODO: improve throughput. Currently limited to 1 write every 3 cycles and read every 2 cycles (plus wb slave latency) -module axi4l_wb_bridge #( +module axil_wb_bridge #( parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 32 )( diff --git a/tests/common/axi4_lite_tb.sv b/lib/tb/axil_wb_bridge_tb.sv similarity index 89% rename from tests/common/axi4_lite_tb.sv rename to lib/tb/axil_wb_bridge_tb.sv index 61124ac..aa32598 100644 --- a/tests/common/axi4_lite_tb.sv +++ b/lib/tb/axil_wb_bridge_tb.sv @@ -1,4 +1,10 @@ -module axi4_lite_tb(); +`include "bh_assert.sv" +`timescale 1ns/1ps + +import bh_assert::bh_assert_equal; +import bh_assert::bh_assert_stats; + +module axil_wb_bridge_tb(); parameter ADDR_WIDTH = 8; parameter DATA_WIDTH = 32; @@ -39,7 +45,7 @@ logic wb_stb_o; logic wb_ack_i; logic wb_cyc_o; -axi4l_wb_bridge #( +axil_wb_bridge #( .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH) ) dut( @@ -91,6 +97,9 @@ always #5 clk <= !clk; initial begin + #10 + bh_assert_stats(); + $finish; end endmodule \ No newline at end of file diff --git a/lib/tb/skidbuffer_tb.sv b/lib/tb/skidbuffer_tb.sv index a91bb91..e8db558 100644 --- a/lib/tb/skidbuffer_tb.sv +++ b/lib/tb/skidbuffer_tb.sv @@ -60,6 +60,7 @@ module skidbuffer_tb(); end end + #10 bh_assert_stats(); $finish; end