brendanhaines/cpu
1
0
Fork 0
mirror of https://gitlab.com/brendanhaines/cpu.git synced 2024-12-26 02:56:52 -07:00
Code Issues Packages Projects Releases Wiki Activity

prevent simulation from printing all writes to regfile

Browse Source
This commit is contained in:
Brendan Haines 2021-07-03 21:02:48 -06:00
parent 34dc20f115
commit cc4101c1f8
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hdl/core.v
View File

@ -546,7 +546,7 @@ always @(posedge clk) begin: pipeline_update
// TODO: should I write if s_wb_stall=1? // TODO: should I write if s_wb_stall=1?
if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin
regfile[r_wb_rd] <= s_wb_data; regfile[r_wb_rd] <= s_wb_data;
$display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data); // $display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
end end
end end
end end