cpu/Makefile

BUILD_DIR = build

# ================
# Hardware options
# ================
# SOURCE_V = $(wildcard hdl/*.v)
# TESTBENCH_V = $(wildcard hdl/tb/*.v)
SOURCE_V = hdl/core.v
TESTBENCH_V = hdl/tb/core_tb.v

# ================
# Software options
# ================
CC = riscv64-linux-gnu-gcc
# CFLAGS = -march=rv32i -mabi=ilp32
CFLAGS = -march=rv64i -mabi=lp64

AS = riscv64-linux-gnu-as
ASFLAGS = $(CFLAGS)

LD = riscv64-linux-gnu-ld
LDFLAGS = -T

all: sim

## Hardware
$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
	iverilog $^ -o $@

## Software
$(BUILD_DIR)/%.o: test/%.S | $(BUILD_DIR)
	$(AS) $(ASFLAGS) $^ -o $@

$(BUILD_DIR)/%.o: test/%.c | $(BUILD_DIR)
	$(CC) $(CFLAGS) $^ -o $@

$(BUILD_DIR)/%.elf: test/%.ld $(BUILD_DIR)/%.o | $(BUILD_DIR)
	$(LD) $(LDFLAGS) $^ -o $@

%.hex: %.elf
	riscv64-linux-gnu-objcopy --target=verilog $< $@

sim: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
	cd $(BUILD_DIR) && ./tb.out


## General
$(BUILD_DIR):
	mkdir -p $(BUILD_DIR)

clean:
	rm -rf $(BUILD_DIR)

.SECONDARY:
.PHONY: all clean sim