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https://gitlab.com/brendanhaines/cpu.git
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56 lines
1.0 KiB
Makefile
56 lines
1.0 KiB
Makefile
BUILD_DIR = build
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# ================
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# Hardware options
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# ================
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# SOURCE_V = $(wildcard hdl/*.v)
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# TESTBENCH_V = $(wildcard hdl/tb/*.v)
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SOURCE_V = hdl/core.v
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TESTBENCH_V = hdl/tb/core_tb.v
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# ================
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# Software options
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# ================
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CC = riscv64-linux-gnu-gcc
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# CFLAGS = -march=rv32i -mabi=ilp32
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CFLAGS = -march=rv64i -mabi=lp64
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AS = riscv64-linux-gnu-as
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ASFLAGS = $(CFLAGS)
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LD = riscv64-linux-gnu-ld
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LDFLAGS = -T
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all: sim
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## Hardware
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$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
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iverilog $^ -o $@
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## Software
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$(BUILD_DIR)/%.o: test/%.S | $(BUILD_DIR)
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$(AS) $(ASFLAGS) $^ -o $@
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$(BUILD_DIR)/%.o: test/%.c | $(BUILD_DIR)
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$(CC) $(CFLAGS) $^ -o $@
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$(BUILD_DIR)/%.elf: test/%.ld $(BUILD_DIR)/%.o | $(BUILD_DIR)
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$(LD) $(LDFLAGS) $^ -o $@
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%.hex: %.elf
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riscv64-linux-gnu-objcopy --target=verilog $< $@
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sim: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
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cd $(BUILD_DIR) && ./tb.out
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## General
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$(BUILD_DIR):
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mkdir -p $(BUILD_DIR)
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clean:
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rm -rf $(BUILD_DIR)
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.SECONDARY:
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.PHONY: all clean sim
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