cpu/Makefile

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BUILD_DIR = build
# ================
# Hardware options
# ================
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# SOURCE_V = $(wildcard hdl/*.v)
# TESTBENCH_V = $(wildcard hdl/tb/*.v)
SOURCE_V = hdl/core.v
TESTBENCH_V = hdl/tb/core_tb.v
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# ================
# Software options
# ================
# SOURCE_C = $(wildcard test/*.c)
SOURCE_C =
SOURCE_AS = $(wildcard test/*.S)
OBJ = $(addprefix $(BUILD_DIR)/, $(notdir $(SOURCE_AS:.S=.o)))
OBJ += $(addprefix $(BUILD_DIR)/, $(notdir $(SOURCE_C:.c=.o)))
CC = riscv64-linux-gnu-gcc-8
# CFLAGS = -march=rv32i -mabi=ilp32
CFLAGS = -march=rv64i -mabi=lp64
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AS = riscv64-linux-gnu-as
ASFLAGS = $(CFLAGS)
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LD = riscv64-linux-gnu-ld
LDFLAGS = -T
all: sim
## Hardware
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$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
iverilog $^ -o $@
## Software
$(BUILD_DIR)/%.o: test/%.S | $(BUILD_DIR)
$(AS) $(ASFLAGS) $^ -o $@
$(BUILD_DIR)/%.o: test/%.c | $(BUILD_DIR)
$(CC) $(CFLAGS) $^ -o $@
$(BUILD_DIR)/%.elf: test/%.ld $(OBJ) | $(BUILD_DIR)
$(LD) $(LDFLAGS) $^ -o $@
%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
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$(BUILD_DIR)/core_tb.vcd: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
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cd $(BUILD_DIR) && ./tb.out
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sim: $(BUILD_DIR)/core_tb.vcd
## General
$(BUILD_DIR):
mkdir -p $(BUILD_DIR)
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clean:
rm -rf $(BUILD_DIR)
.SECONDARY:
.PHONY: all clean sim