cpu/tests/test_basic/Makefile

all: verify

TESTBENCH_V = $(wildcard *tb.sv)
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
SOURCE_V += $(wildcard ../../lib/*.v ../../lib/*.sv)
LOGS = $(TESTBENCH_V:.sv=.log)

SOURCE_C = $(wildcard *.c)
SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o))

# Software compilation
CC = riscv64-linux-gnu-gcc
CFLAGS = -march=rv32i -mabi=ilp32

CPPFLAGS =

AS = riscv64-linux-gnu-as
ASFLAGS = -march=rv32i -mabi=ilp32

LD = riscv64-linux-gnu-ld
LDFLAGS = -melf32lriscv_ilp32

# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
# $(info $$SOURCE_V is [${SOURCE_V}])
# $(info $$LOGS is [${LOGS}])
# $(info $$SOURCE_C is [${SOURCE_C}])
# $(info $$SOURCE_AS is [${SOURCE_AS}])
# $(info $$OBJ is [${OBJ}])

%.o: %.S
	$(AS) $(ASFLAGS) $^ -o $@

%.o: %.c
%.s: %.c
	$(CC) $(CPPFLAGS) $(CFLAGS) -S $^ -o $@

%.elf: %.ld $(OBJ)
	$(LD) $(LDFLAGS) -T $^ -o $@

%.hex: %.elf
	riscv64-linux-gnu-objcopy --target=verilog $< $@

# Hardware compilation
%.out: %.sv $(SOURCE_V)
	iverilog -g2012 -o $@ $^ -Y .sv -I ../../lib

# Run test
%.vcd %.log: %.out %.hex
	./$< | tee $(patsubst %.out, %.log, $<)

verify: $(LOGS)
	@! grep -q "ERROR" $^
	@grep -q "SUCCESS" $^

clean:
	rm -rf *.vcd *.log *.out *.hex

.SECONDARY: %.log %.vcd
.PHONY: all clean verify