cpu/tests/test_basic/Makefile

62 lines
1.2 KiB
Makefile
Raw Permalink Normal View History

2021-08-11 00:18:46 -06:00
all: verify
TESTBENCH_V = $(wildcard *tb.sv)
SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
SOURCE_V += $(wildcard ../../lib/*.v ../../lib/*.sv)
2021-08-11 00:18:46 -06:00
LOGS = $(TESTBENCH_V:.sv=.log)
2021-09-08 23:43:15 -06:00
SOURCE_C = $(wildcard *.c)
2021-08-11 00:18:46 -06:00
SOURCE_AS = $(wildcard *.S)
OBJ = $(notdir $(SOURCE_AS:.S=.o))
OBJ += $(notdir $(SOURCE_C:.c=.o))
2022-11-19 18:41:25 -07:00
# Software compilation
2021-09-08 23:43:15 -06:00
CC = riscv64-linux-gnu-gcc
2021-09-08 23:17:34 -06:00
CFLAGS = -march=rv32i -mabi=ilp32
2021-08-11 00:18:46 -06:00
CPPFLAGS =
AS = riscv64-linux-gnu-as
2021-09-08 23:43:15 -06:00
ASFLAGS = -march=rv32i -mabi=ilp32
2021-08-11 00:18:46 -06:00
LD = riscv64-linux-gnu-ld
2021-09-08 23:17:34 -06:00
LDFLAGS = -melf32lriscv_ilp32
2021-08-11 00:18:46 -06:00
# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
# $(info $$SOURCE_V is [${SOURCE_V}])
# $(info $$LOGS is [${LOGS}])
# $(info $$SOURCE_C is [${SOURCE_C}])
# $(info $$SOURCE_AS is [${SOURCE_AS}])
# $(info $$OBJ is [${OBJ}])
%.o: %.S
$(AS) $(ASFLAGS) $^ -o $@
%.o: %.c
2021-09-08 23:43:15 -06:00
%.s: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) -S $^ -o $@
2021-08-11 00:18:46 -06:00
%.elf: %.ld $(OBJ)
2021-09-08 23:17:34 -06:00
$(LD) $(LDFLAGS) -T $^ -o $@
2021-08-11 00:18:46 -06:00
%.hex: %.elf
riscv64-linux-gnu-objcopy --target=verilog $< $@
2022-11-19 18:41:25 -07:00
# Hardware compilation
2021-08-11 00:18:46 -06:00
%.out: %.sv $(SOURCE_V)
2022-12-01 01:05:39 -07:00
iverilog -g2012 -o $@ $^ -Y .sv -I ../../lib
2021-08-11 00:18:46 -06:00
2022-11-19 18:41:25 -07:00
# Run test
2021-08-11 00:18:46 -06:00
%.vcd %.log: %.out %.hex
./$< | tee $(patsubst %.out, %.log, $<)
verify: $(LOGS)
@! grep -q "ERROR" $^
@grep -q "SUCCESS" $^
2021-08-11 00:18:46 -06:00
clean:
rm -rf *.vcd *.log *.out *.hex
.SECONDARY: %.log %.vcd
.PHONY: all clean verify