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https://gitlab.com/brendanhaines/cpu.git
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62 lines
1.2 KiB
Makefile
62 lines
1.2 KiB
Makefile
all: verify
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TESTBENCH_V = $(wildcard *tb.sv)
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SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
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SOURCE_V += $(wildcard ../../lib/*.v ../../lib/*.sv)
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LOGS = $(TESTBENCH_V:.sv=.log)
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SOURCE_C = $(wildcard *.c)
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SOURCE_AS = $(wildcard *.S)
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OBJ = $(notdir $(SOURCE_AS:.S=.o))
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OBJ += $(notdir $(SOURCE_C:.c=.o))
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# Software compilation
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CC = riscv64-linux-gnu-gcc
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CFLAGS = -march=rv32i -mabi=ilp32
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CPPFLAGS =
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AS = riscv64-linux-gnu-as
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ASFLAGS = -march=rv32i -mabi=ilp32
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LD = riscv64-linux-gnu-ld
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LDFLAGS = -melf32lriscv_ilp32
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# $(info $$TESTBENCH_V is [${TESTBENCH_V}])
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# $(info $$SOURCE_V is [${SOURCE_V}])
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# $(info $$LOGS is [${LOGS}])
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# $(info $$SOURCE_C is [${SOURCE_C}])
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# $(info $$SOURCE_AS is [${SOURCE_AS}])
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# $(info $$OBJ is [${OBJ}])
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%.o: %.S
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$(AS) $(ASFLAGS) $^ -o $@
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%.o: %.c
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%.s: %.c
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$(CC) $(CPPFLAGS) $(CFLAGS) -S $^ -o $@
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%.elf: %.ld $(OBJ)
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$(LD) $(LDFLAGS) -T $^ -o $@
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%.hex: %.elf
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riscv64-linux-gnu-objcopy --target=verilog $< $@
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# Hardware compilation
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%.out: %.sv $(SOURCE_V)
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iverilog -g2012 -o $@ $^ -Y .sv -I ../../lib
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# Run test
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%.vcd %.log: %.out %.hex
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./$< | tee $(patsubst %.out, %.log, $<)
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verify: $(LOGS)
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@! grep -q "ERROR" $^
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@grep -q "SUCCESS" $^
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clean:
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rm -rf *.vcd *.log *.out *.hex
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.SECONDARY: %.log %.vcd
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.PHONY: all clean verify
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