add basic example

hdl/.gitignore

@@ -0,0 +1,6 @@
+*.out
+*.vcd
+*.blif
+*.asc
+*.rpt
+*.bin

hdl/Makefile

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+PROJ = top
+PIN_DEF = pins.pcf
+DEVICE = hx8k
+PACKAGE = ct256
+
+all: $(PROJ).rpt $(PROJ).bin
+
+%.blif: %.v
+	yosys -p 'synth_ice40 -top top -blif $@' $(wildcard *.v)
+	# yosys -p 'synth_ice40 -top top -blif $@' $<
+
+%.asc: $(PIN_DEF) %.blif
+	arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -P $(PACKAGE) -o $@ -p $^
+
+%.bin: %.asc
+	icepack $< $@
+
+%.rpt: %.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+prog: $(PROJ).bin
+	iceprog $<
+
+sudo-prog: $(PROJ).bin
+	@echo 'Executing prog as root!!!'
+	sudo iceprog $<
+
+tb.out: $(wildcard *.v) $(wildcard tb/*.v)
+	iverilog $^ -o $@
+
+sim: tb.out
+	./tb.out
+
+clean:
+	rm -rf $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin tb.out tb.vcd
+
+.SECONDARY:
+.PHONY: all prog clean sim

hdl/counter.v

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+module counter #(
+    parameter BITS = 8
+)(
+    input clk,
+    input reset,
+    output reg [BITS-1:0] y
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        y <= 0;
+    end else begin
+        y <= y + 1;
+    end
+end
+
+endmodule

hdl/pins.pcf

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+set_io led[0]   E4
+set_io led[1]   B2
+set_io led[2]   F5
+set_io led[3]   B1
+set_io led[4]   C1
+set_io led[5]   C2
+set_io led[6]   F4
+set_io led[7]   D2
+set_io clk      G5
+set_io n_reset  D1

hdl/tb/tb.gtkw

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+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Fri Jul  2 06:30:08 2021
+[*]
+[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb.vcd"
+[dumpfile_mtime] "Fri Jul  2 06:30:05 2021"
+[dumpfile_size] 29504
+[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw"
+[timestart] 0
+[size] 1920 1052
+[pos] -1 -1
+*-19.000000 765000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb.
+[treeopen] tb.top.
+[sst_width] 233
+[signals_width] 279
+[sst_expanded] 1
+[sst_vpaned_height] 656
+@28
+tb.clk
+tb.reset
+@c08022
+tb.led[7:0]
+@28
+(0)tb.led[7:0]
+(1)tb.led[7:0]
+(2)tb.led[7:0]
+(3)tb.led[7:0]
+(4)tb.led[7:0]
+(5)tb.led[7:0]
+(6)tb.led[7:0]
+(7)tb.led[7:0]
+@1401200
+-group_end
+[pattern_trace] 1
+[pattern_trace] 0

hdl/tb/tb.v

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+// Author:  Brendan Haines
+// Date:    2021-07-02
+
+`timescale 1ns/1ps
+
+module tb();
+
+reg clk, reset;
+wire [7:0] led;
+
+top top(
+    .clk(clk),
+    .n_reset(~reset),
+    .led(led)
+);
+
+always #5 clk = ~clk;
+
+initial begin
+    $dumpfile("tb.vcd");
+    $dumpvars(0, tb);
+
+    clk = 0;
+    reset = 1;
+
+    #10
+    reset = 0;
+
+    #2560
+    // #2560
+    $display("----------");
+    $display("Finished simulation.");
+    $display("Simulation time:\t%d ns", $realtime);
+    $finish;
+end
+
+endmodule

hdl/top.v

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+// Author:  Brendan Haines
+// Date:    2020-05-04
+
+module top(
+    input clk,
+    input n_reset,
+    output [7:0] led
+);
+
+counter #(
+    .BITS(8)
+) count(
+    .clk(clk),
+    .reset(~n_reset),
+    .y(led)
+);
+
+endmodule