mirror of
https://gitlab.com/brendanhaines/ice40.git
synced 2024-09-19 20:36:12 -06:00
17 lines
251 B
Verilog
17 lines
251 B
Verilog
module counter #(
|
|
parameter BITS = 8
|
|
)(
|
|
input clk,
|
|
input reset,
|
|
output reg [BITS-1:0] y
|
|
);
|
|
|
|
always @(posedge clk or posedge reset) begin
|
|
if (reset) begin
|
|
y <= 0;
|
|
end else begin
|
|
y <= y + 1;
|
|
end
|
|
end
|
|
|
|
endmodule |