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explicitly specify sources

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Brendan Haines 2021-07-02 00:41:37 -06:00
parent 30dac2760c
commit 0ec0c32d87
1 changed files with 5 additions and 2 deletions
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7
hdl/Makefile
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@ -3,10 +3,13 @@ PIN_DEF = pins.pcf
DEVICE = hx8k DEVICE = hx8k
PACKAGE = ct256 PACKAGE = ct256
SOURCE_V = $(wildcard *.v)
TESTBENCH_V = $(wildcard tb/*.v)
all: $(PROJ).rpt $(PROJ).bin all: $(PROJ).rpt $(PROJ).bin
%.blif: %.v %.blif: %.v
yosys -p 'synth_ice40 -top top -blif $@' $(wildcard *.v) yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
# yosys -p 'synth_ice40 -top top -blif $@' $< # yosys -p 'synth_ice40 -top top -blif $@' $<
%.asc: $(PIN_DEF) %.blif %.asc: $(PIN_DEF) %.blif
@ -25,7 +28,7 @@ sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!' @echo 'Executing prog as root!!!'
sudo iceprog $< sudo iceprog $<
tb.out: $(wildcard *.v) $(wildcard tb/*.v) tb.out: $(SOURCE_V) $(TESTBENCH_V)
iverilog $^ -o $@ iverilog $^ -o $@
sim: tb.out sim: tb.out