This website requires JavaScript.
Explore
Help
Sign In
brendanhaines
/
cpu
Watch
1
Star
0
Fork
0
You've already forked cpu
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
2
Commits
2
Branches
0
Tags
2ad82e2b90c62709574ceb3fad498c4a766285b6
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Brendan Haines
2ad82e2b90
add test assembly file
2020-09-27 18:04:08 -06:00
asm
add test assembly file
2020-09-27 18:04:08 -06:00
hdl
add test assembly file
2020-09-27 18:04:08 -06:00
sim
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitignore
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
.gitmodules
add test assembly file
2020-09-27 18:04:08 -06:00
Makefile
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
pins.ucf
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
project.cfg
initial commit. Non-working due to newly added MEM backpressure signal
2020-09-27 16:04:16 -06:00
Description
RISC-V CPU
525
KiB
Languages
Verilog
44.7%
SystemVerilog
36.6%
Assembly
15.1%
Makefile
3.5%
