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69e4ea9204
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clean up core_tb.v a little
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2021-07-02 03:20:38 -06:00 |
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07d317eb6e
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add trailing NOP instructions so non-initialized memory doesn't cause issues
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2021-07-02 03:14:37 -06:00 |
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9ff977c1be
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partially working with common address space. loading of .data section has been disabled
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2021-07-02 03:11:50 -06:00 |
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17a95b58c8
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fix the code issues I just introduced
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2021-07-02 02:39:43 -06:00 |
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0a9b182ef7
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BAD CODE: testing that CI pipeline catches verilog issues
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2021-07-02 02:39:13 -06:00 |
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e32e451e60
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update waveform view
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2021-07-02 02:03:32 -06:00 |
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5c59c97797
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build software project in same makefile as hardware project
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2021-07-02 02:03:32 -06:00 |
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180f05fb0a
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shift to iverilog + gtkwave for simulation
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2021-07-02 02:03:32 -06:00 |
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d58661e289
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add more extensive memory test
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2020-11-14 23:36:23 -07:00 |
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6d39c01740
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fix testbench so both load and store work
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2020-11-14 23:21:33 -07:00 |
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4a25ca6def
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fix issue of jumping to address 0
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2020-11-14 23:04:24 -07:00 |
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caf9a6f4f7
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separate .text and .data for instruction and data memory
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2020-11-10 00:19:42 -07:00 |
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32d0a2dcaa
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display more data to simplify verification
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2020-11-09 23:38:22 -07:00 |
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1290418aa3
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properly flushes pipeline after jump
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2020-11-06 23:18:37 -07:00 |
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2c24c19a72
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passes quick tests for: lui, addi, add, sub, and, or, xor, andi. jump works but does not link
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2020-10-11 23:03:14 -06:00 |
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24171412bd
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successfully using assembler to generate .hex rather than writing straight machine code
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2020-09-27 18:38:35 -06:00 |
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275f66bf24
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fix typo in core_tb.v assembly
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2020-09-27 18:07:12 -06:00 |
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63ed8ace80
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initial commit. Non-working due to newly added MEM backpressure signal
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2020-09-27 16:04:16 -06:00 |
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