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e3c52db637
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make sim will now fail if test hits fail state
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2021-07-03 20:59:03 -06:00 |
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d4ed4ec2bc
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add ability to wait for memory writes
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2021-07-03 19:39:22 -06:00 |
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5e87ea0c75
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fix loading of sectios other than .text and get rid of massive sed chain for .hex generation
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2021-07-02 04:47:40 -06:00 |
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9031b5b4c5
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working load/store word with byte addressed memory
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2021-07-02 04:32:25 -06:00 |
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35423ce4af
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works with 8bit addressed memory (rather than word addressed)
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2021-07-02 04:22:33 -06:00 |
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57e745b336
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more clean up and reorganization from memory restructuring
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2021-07-02 03:28:21 -06:00 |
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9ff977c1be
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partially working with common address space. loading of .data section has been disabled
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2021-07-02 03:11:50 -06:00 |
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e32e451e60
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update waveform view
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2021-07-02 02:03:32 -06:00 |
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180f05fb0a
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shift to iverilog + gtkwave for simulation
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2021-07-02 02:03:32 -06:00 |
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