cpu/lib/tb/skidbuffer_tb.sv

147 lines
3.7 KiB
Systemverilog

`timescale 1ns/1ps
// import bh_assert::*;
module skidbuffer_tb();
int bh_assert_pass_count = 0;
int bh_assert_fail_count = 0;
int bh_assert_warn_count = 0;
localparam BH_ASSERT_LOG_LEVEL_FAIL = 0;
localparam BH_ASSERT_LOG_LEVEL_ASSERT = 1;
localparam BH_ASSERT_LOG_LEVEL_WARN = 2;
localparam BH_ASSERT_LOG_LEVEL_INFO = 3;
logic bh_assert_log_level = BH_ASSERT_LOG_LEVEL_WARN; // 0 = errors only, 1 = all assertions, 2 = warnings, 3 = info
localparam COLOR_RED = "\033[31m";
localparam COLOR_YELLOW = "\033[33m";
localparam COLOR_GREEN = "\033[32m";
localparam COLOR_NORMAL = "\033[0;39m";
task bh_assert_equal(int val, int expected, string description);
// display results
$timeformat(-9, 2, " ns", 20);
$display(
"%t: %s: %d %s %d - %s",
$time,
val == expected ? {COLOR_GREEN, "PASS", COLOR_NORMAL} : {COLOR_RED, "FAIL", COLOR_NORMAL},
val,
val == expected ? "==" : "!=",
expected,
description
);
// update statistics
if (val == expected) begin
bh_assert_pass_count = bh_assert_pass_count + 1;
end else begin
bh_assert_fail_count = bh_assert_fail_count + 1;
end
endtask
task bh_assert_stats;
$timeformat(-9, 2, " ns", 20);
$display("%t: DONE: %1d pass, %1d fail, %1d warn", $time, bh_assert_pass_count, bh_assert_fail_count, bh_assert_warn_count);
if (bh_assert_pass_count + bh_assert_fail_count == 0) begin
$display("%sERROR%s: no assertions found", COLOR_YELLOW, COLOR_NORMAL);
// TODO: error in a better way?
end else if (bh_assert_fail_count > 0) begin
$display("%sERROR%s: some tests failed", COLOR_RED, COLOR_NORMAL);
end else begin
$display("%sSUCCESS%s: all tests passed", COLOR_GREEN, COLOR_NORMAL);
end
endtask
task bh_info(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_INFO) begin
$display("%t: INFO: %s", $time, description);
end
endtask
task bh_warn(string description);
if (bh_assert_log_level >= BH_ASSERT_LOG_LEVEL_WARN) begin
$display("%t: %sWARN%s: %s", $time, COLOR_YELLOW, COLOR_NORMAL, description);
end
bh_assert_warn_count = bh_assert_warn_count + 1;
endtask
parameter WIDTH = 15;
parameter TEST_LIST_LENGTH = 256;
logic clk = 0;
logic reset = 1;
logic [WIDTH-1:0] in;
logic in_valid = 0;
wire in_ready;
wire [WIDTH-1:0] out;
wire out_valid;
logic out_ready = 0;
skidbuffer #(
.WIDTH(WIDTH)
) dut (
.clk(clk),
.reset(reset),
.in(in),
.in_valid(in_valid),
.in_ready(in_ready),
.out(out),
.out_valid(out_valid),
.out_ready(out_ready)
);
integer i = 0;
integer in_count = 0;
integer out_count = 0;
logic [WIDTH-1:0] in_list [0:TEST_LIST_LENGTH-1];
assign in = in_list[in_count];
always #5 clk = !clk;
initial begin
$dumpfile("skidbuffer_tb.vcd");
$dumpvars(0, skidbuffer_tb);
for (i=0; i<TEST_LIST_LENGTH; i=i+1) begin
in_list[i] = $urandom();
end
#10
reset = 0;
while (out_count < TEST_LIST_LENGTH) begin
#10
if (!in_valid || (in_valid && in_ready)) begin
in_valid = $urandom_range(1);
end
if (!out_ready || (out_ready && out_valid)) begin
out_ready = $urandom_range(1);
end
end
bh_assert_stats();
$finish;
end
always @(posedge clk) begin
if (reset == 0 && in_valid && in_ready) begin
in_count <= in_count + 1;
end
if (reset == 0 && out_valid && out_ready) begin
bh_assert_equal(out, in_list[out_count], $sformatf("Output value [%3d]", out_count));
bh_warn("hello warning");
bh_info("hello info");
out_count <= out_count + 1;
end
end
wire [WIDTH-1:0] out_correct;
assign out_correct = in_list[out_count];
endmodule