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working load/store word with byte addressed memory

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This commit is contained in:
Brendan Haines
2021-07-02 04:32:25 -06:00
parent 35423ce4af
commit 9031b5b4c5
3 changed files with 46 additions and 30 deletions
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11
hdl/tb/core_tb.gtkw
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@ -1,15 +1,15 @@
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 10:10:54 2021
[*] Fri Jul 2 10:31:57 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Fri Jul 2 10:09:55 2021"
[dumpfile_size] 53841
[dumpfile_mtime] "Fri Jul 2 10:31:52 2021"
[dumpfile_size] 685027
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 0
[timestart] 703450
[size] 1920 1052
[pos] -1 -1
*-13.000000 12780 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-14.000000 747270 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289
@ -25,7 +25,6 @@ core_tb.reset
-
@22
core_tb.mem_data_addr[31:0]
core_tb.mem_data_idx[31:0]
core_tb.mem_data_rdata[31:0]
core_tb.mem_data_wdata[31:0]
@28

62
hdl/tb/core_tb.v
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@ -40,32 +40,50 @@ end
// Data memory
wire [31:0] mem_data_addr;
wire [31:0] mem_data_idx = (mem_data_addr) >> 2;
wire [31:0] mem_data_rdata = mem_data_idx < MEM_LENGTH ? mem[mem_data_idx] : DATA_INVALID;
reg [31:0] mem_data_rdata;
wire [31:0] mem_data_wdata;
wire [3:0] mem_data_wmask;
wire mem_data_we;
// always @(posedge clk) begin
// if (mem_data_idx < MEM_LENGTH && mem_data_idx >= MEM_ROM_LENGTH) begin
// if (mem_data_we) begin
// if (mem_data_wmask[0]) begin
// mem[mem_data_idx][7:0] <= mem_data_wdata[7:0];
// end
// if (mem_data_wmask[1]) begin
// mem[mem_data_idx][15:8] <= mem_data_wdata[15:8];
// end
// if (mem_data_wmask[2]) begin
// mem[mem_data_idx][23:16] <= mem_data_wdata[23:16];
// end
// if (mem_data_wmask[3]) begin
// mem[mem_data_idx][31:24] <= mem_data_wdata[31:24];
// end
// end
// end else begin
// // ignore illegal writes
// end
// end
always @(*) begin
if (mem_data_addr < MEM_LENGTH - 3) begin
mem_data_rdata[ 7: 0] = mem[mem_data_addr+0];
if (mem_data_addr[0] == 0) begin
mem_data_rdata[15: 8] = mem[mem_data_addr+1];
if (mem_data_addr[1] == 0) begin
mem_data_rdata[23:16] = mem[mem_data_addr+2];
mem_data_rdata[31:24] = mem[mem_data_addr+3];
end else begin
mem_data_rdata[31:16] = 0;
end
end else begin
mem_data_rdata[31:8] = 0;
end
end else begin
mem_data_rdata = DATA_INVALID;
end
end
always @(posedge clk) begin
if (mem_data_we) begin
if (mem_data_addr < MEM_LENGTH && mem_data_addr >= MEM_ROM_LENGTH) begin
if (mem_data_wmask[0]) begin
mem[mem_data_addr+0] <= mem_data_wdata[7:0];
end
if (mem_data_wmask[1]) begin
mem[mem_data_addr+1] <= mem_data_wdata[15:8];
end
if (mem_data_wmask[2]) begin
mem[mem_data_addr+2] <= mem_data_wdata[23:16];
end
if (mem_data_wmask[3]) begin
mem[mem_data_addr+3] <= mem_data_wdata[31:24];
end
end else begin
// ignore illegal writes
end
end
end
// Main control