working assertion lib

2022-12-01 01:03:23 -07:00
parent ebc3b22ac7
commit 38a91579ec
4 changed files with 38 additions and 85 deletions
--- a/lib/tb/Makefile
+++ b/lib/tb/Makefile
@@ -6,7 +6,7 @@ LOGS = $(TESTBENCH_V:.sv=.log)

 # Hardware compilation
 %.out: %.sv $(SOURCE_V)
-	iverilog -g2012 -o $@ $^
+	iverilog -g2012 -o $@ $< -y ../ -Y .sv -I ../

 # Run test
 %.vcd %.log: %.out