display more data to simplify verification

hdl/tb/core_tb.v

@@ -1,4 +1,4 @@
-`timescale 1 ns / 1 ps 
+`timescale 500 ps / 1 ps 
 
 module core_tb();
 
@@ -39,15 +39,15 @@ initial begin
     clk = 0;
     reset = 1;
     
-    #20
+    #10
     reset = 0;
     
-    #5000
+    #1000
     reset = 1;
     $stop;
 end
 
-always #10 clk  = !clk;
+always #2 clk  = !clk;
 
 core dut(
     .clk(clk),