diff --git a/hdl/core.v b/hdl/core.v
index 2310b5b..c9f9780 100644
--- a/hdl/core.v
+++ b/hdl/core.v
@@ -298,7 +298,7 @@ always @(*) begin
             (((r_wb_rd == s_id_rs1) && (s_id_rs1 != 0)) ||
             ((r_wb_rd == s_id_rs2) && (s_id_rs2 != 0))));
 
-    if (s_id_invalid) begin
+    if (s_id_invalid & r_id_valid) begin
         $display("%0t:\tInvalid instruction at PC=0x%h", $time, r_id_pc);
         s_id_aluop      = 3'hx;
     end
@@ -507,6 +507,7 @@ always @(posedge clk) begin: pipeline_update
             // TODO: should I write if s_wb_stall=1?
             if (r_wb_rd != 0 && s_wb_write && r_wb_valid) begin
                 regfile[r_wb_rd] <= s_wb_data;
+                $display("%0t:\tPC=0x%h\tx%02d=0x%h", $time, r_id_pc, r_wb_rd, s_wb_data);
             end
     end
 end
diff --git a/hdl/tb/core_tb.v b/hdl/tb/core_tb.v
index d72645e..d60b06a 100644
--- a/hdl/tb/core_tb.v
+++ b/hdl/tb/core_tb.v
@@ -1,4 +1,4 @@
-`timescale 1 ns / 1 ps 
+`timescale 500 ps / 1 ps 
 
 module core_tb();
 
@@ -39,15 +39,15 @@ initial begin
     clk = 0;
     reset = 1;
     
-    #20
+    #10
     reset = 0;
     
-    #5000
+    #1000
     reset = 1;
     $stop;
 end
 
-always #10 clk  = !clk;
+always #2 clk  = !clk;
 
 core dut(
     .clk(clk),