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Brendan Haines
2025-08-29 00:53:21 -06:00
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# RISC-V CPU # RISC-V CPU
Short Term To Do: Short Term To Do:
* add stalls for memory access -[ ] add stalls for memory access
* use AXI for memory access (depends on AXIL memory module for test) -[ ] use AXI for memory access (depends on AXIL memory module for test)
* add tests for non-pipelined case -[ ] add tests for non-pipelined case
* get C working (may depend on memory stalls) -[ ] get C working (may depend on memory stalls)
Desired features: Desired features:
* 1- or 5-stage pipeline selectable via parameter -[ ] 1- or 5-stage pipeline selectable via parameter
* AXI-lite Master for both instruction and data memory -[ ] AXI-lite Master for both instruction and data memory
* 32, 64, (or 128?) bit word size -[ ] 32, 64, (or 128?) bit word size
* floating point -[ ] floating point
* multiplication -[ ] multiplication
* division -[ ] division
* instruction and data caches -[ ] instruction and data caches
* JTAG debug probe -[ ] JTAG debug probe
## Installation
Run `setup.sh` to install GCC
## Resources ## Resources
* [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en) * [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)