From 1a135b596665ea8b9f2b13ce081c152a7c178b5c Mon Sep 17 00:00:00 2001 From: Brendan Haines Date: Fri, 29 Aug 2025 00:53:21 -0600 Subject: [PATCH] update README.md --- README.md | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/README.md b/README.md index 9aa1154..0ac8cab 100644 --- a/README.md +++ b/README.md @@ -1,23 +1,20 @@ # RISC-V CPU Short Term To Do: -* add stalls for memory access -* use AXI for memory access (depends on AXIL memory module for test) -* add tests for non-pipelined case -* get C working (may depend on memory stalls) +-[ ] add stalls for memory access +-[ ] use AXI for memory access (depends on AXIL memory module for test) +-[ ] add tests for non-pipelined case +-[ ] get C working (may depend on memory stalls) Desired features: -* 1- or 5-stage pipeline selectable via parameter -* AXI-lite Master for both instruction and data memory -* 32, 64, (or 128?) bit word size -* floating point -* multiplication -* division -* instruction and data caches -* JTAG debug probe - -## Installation -Run `setup.sh` to install GCC +-[ ] 1- or 5-stage pipeline selectable via parameter +-[ ] AXI-lite Master for both instruction and data memory +-[ ] 32, 64, (or 128?) bit word size +-[ ] floating point +-[ ] multiplication +-[ ] division +-[ ] instruction and data caches +-[ ] JTAG debug probe ## Resources * [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)