2020-09-27 18:04:08 -06:00
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.global _start
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.text
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_start:
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2020-10-03 13:49:14 -06:00
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# NOTE: nop required because cpu currently does not detect when something is needed from a later stage of the pipeline.
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2020-10-11 23:03:14 -06:00
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# 4 clocks allows one instruction to finish before the next reads the regfile
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# AUIPC
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# JAL
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# JALR
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# SLTI
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# SLTUI
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# SLL
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# SRL
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# SRA
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# SLT
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# SLTU
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2020-10-03 13:49:14 -06:00
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# lui
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2020-10-11 23:36:11 -06:00
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lui x1, 0xfedcb # x1 = 0xfedcb000
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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# addi
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2020-10-11 23:36:11 -06:00
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addi x1, x1, 0x789 # x1 = 0xfedcb789
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addi x2, x0, -1 # x2 = 0xffffffff
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2020-10-03 13:49:14 -06:00
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nop
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nop
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2020-10-11 23:36:11 -06:00
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addi x3, x1, -0x777 # x3 = 0xfedcb012
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2020-10-11 23:03:14 -06:00
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nop
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nop
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nop
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2020-10-03 13:49:14 -06:00
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# add
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2020-10-11 23:36:11 -06:00
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add x4, x1, x2 # x4 = 0xfedcb788
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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# sub
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2020-10-11 23:36:11 -06:00
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sub x5, x1, x3 # x5 = 0x00000777
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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# and
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2020-10-11 23:36:11 -06:00
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and x6, x1, x2 # x6 = 0xfedcb789
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and x7, x1, x0 # x7 = 0x00000000
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and x8, x4, x3 # x8 = 0xfedcb000
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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# or
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2020-10-11 23:36:11 -06:00
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or x9, x1, x2 # x9 = 0xffffffff
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2020-10-11 23:03:14 -06:00
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or x10, x1, x0 # x10 = 0xfedcb789
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or x11, x4, x3 # x11 = 0x0xfedcb79a
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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2020-10-11 23:03:14 -06:00
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# xor
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xor x12, x1, x2 # x12 = 0x01234876
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xor x13, x1, x1 # x13 = 0x00000000
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xor x14, x0, x2 # x14 = 0xffffffff
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nop
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nop
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nop
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# andi
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andi x15, x2, -1348 # x15 = 0xfffffabc -1348 = 0xfffffabc
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andi x16, x2, 0x123 # x16 = 0x00000123
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andi x17, x1, -1645 # x17 = 0xfedcb181 -1645 = 0xfffff993
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nop
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nop
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nop
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2020-10-11 23:06:29 -06:00
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# ori
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ori x18, x2, 0x000 # x18 = 0xffffffff
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ori x19, x0, 0x768 # x19 = 0x768
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ori x20, x1, 0x7ff # x20 = 0xfedcb7ff
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nop
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nop
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nop
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2020-10-11 23:03:14 -06:00
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2020-10-11 23:09:08 -06:00
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# xori
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xori x21, x2, 0x123 # x21 = 0xfffffedc
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xori x22, x1, 0x788 # x22 = 0xfedcb001
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xori x23, x0, 0x788 # x23 = 0x00000788
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nop
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nop
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nop
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2020-10-03 13:49:14 -06:00
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2020-10-11 23:36:11 -06:00
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# slli
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slli x24, x23, 4 # x24 = 0x00007880
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slli x25, x2, 1 # x25 = 0xfffffffe
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slli x26, x2, 63 # x26 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
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slli x27, x2, 31 # x27 = 0x80000000
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nop
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nop
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nop
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# srli
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srli x28, x23, 4 # x28 = 0x00000078
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srli x29, x2, 1 # x29 = 0x7fffffff
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srli x30, x2, 63 # x30 = 0x00000000 // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
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srli x3, x2, 31 # x3 = 0x00000001
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nop
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nop
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nop
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# srai
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srai x4, x23, 4 # x4 = 0x00000078 // fails
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srai x5, x2, 1 # x5 = 0xffffffff
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srai x6, x2, 63 # x6 = 0xffffffff // NOTE: I would expect GCC to throw an error here. It tolerates up to 63 bit shift despite assembling for 32b
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srai x7, x2, 31 # x7 = 0xffffffff
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nop
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nop
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nop
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2020-10-03 13:49:14 -06:00
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2020-10-11 23:03:14 -06:00
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# counter and infinite loop
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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2020-10-11 23:36:11 -06:00
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addi x31, x0, 1 # x1 = 1
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2020-09-27 18:04:08 -06:00
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2020-09-27 18:38:35 -06:00
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loop:
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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2020-10-11 23:36:11 -06:00
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addi x31, x31, 1 # increment x1
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2020-10-03 13:49:14 -06:00
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nop
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nop
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nop
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j loop # loop forever
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nop
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nop
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nop
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nop
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nop
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nop
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2020-09-27 18:38:35 -06:00
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2020-09-27 18:04:08 -06:00
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.data
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