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37 lines
488 B
Verilog
37 lines
488 B
Verilog
// Author: Brendan Haines
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// Date: 2021-07-02
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`timescale 1ns/1ps
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module tb();
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reg clk, reset;
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wire [7:0] led;
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top top(
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.clk(clk),
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.n_reset(~reset),
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.led(led)
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);
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always #5 clk = ~clk;
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initial begin
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$dumpfile("tb.vcd");
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$dumpvars(0, tb);
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clk = 0;
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reset = 1;
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#10
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reset = 0;
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#2560
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// #2560
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$display("----------");
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$display("Finished simulation.");
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$display("Simulation time:\t%d ns", $realtime);
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$finish;
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end
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endmodule |