use separate build directory

.gitignore

@@ -0,0 +1 @@
+build

Makefile

@@ -2,13 +2,14 @@ PROJ = top
 PIN_DEF = pins.pcf
 DEVICE = hx8k
 PACKAGE = ct256
+BUILD_DIR = build
 
-SOURCE_V = $(wildcard *.v)
+SOURCE_V = $(wildcard hdl/*.v)
-TESTBENCH_V = $(wildcard tb/*.v)
+TESTBENCH_V = $(wildcard hdl/tb/*.v)
 
-all: $(PROJ).rpt $(PROJ).bin
+all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
 
-%.blif: %.v
+$(BUILD_DIR)/%.blif: hdl/%.v
 	yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
 	# yosys -p 'synth_ice40 -top top -blif $@' $<
 
@@ -28,14 +29,17 @@ sudo-prog: $(PROJ).bin
 	@echo 'Executing prog as root!!!'
 	sudo iceprog $<
 
-tb.out: $(SOURCE_V) $(TESTBENCH_V)
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
+$(BUILD_DIR)/tb.out: $(BUILD_DIR) $(SOURCE_V) $(TESTBENCH_V)
 	iverilog $^ -o $@
 
-sim: tb.out
+sim: $(BUILD_DIR)/tb.out
-	./tb.out
+	$(BUILD_DIR)/tb.out
 
 clean:
-	rm -rf $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin tb.out tb.vcd
+	rm -rf $(BUILD_DIR)
 
 .SECONDARY:
 .PHONY: all prog clean sim