use separate build directory

hdl/Makefile

@@ -1,41 +0,0 @@
-PROJ = top
-PIN_DEF = pins.pcf
-DEVICE = hx8k
-PACKAGE = ct256
-
-SOURCE_V = $(wildcard *.v)
-TESTBENCH_V = $(wildcard tb/*.v)
-
-all: $(PROJ).rpt $(PROJ).bin
-
-%.blif: %.v
-	yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
-	# yosys -p 'synth_ice40 -top top -blif $@' $<
-
-%.asc: $(PIN_DEF) %.blif
-	arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -P $(PACKAGE) -o $@ -p $^
-
-%.bin: %.asc
-	icepack $< $@
-
-%.rpt: %.asc
-	icetime -d $(DEVICE) -mtr $@ $<
-
-prog: $(PROJ).bin
-	iceprog $<
-
-sudo-prog: $(PROJ).bin
-	@echo 'Executing prog as root!!!'
-	sudo iceprog $<
-
-tb.out: $(SOURCE_V) $(TESTBENCH_V)
-	iverilog $^ -o $@
-
-sim: tb.out
-	./tb.out
-
-clean:
-	rm -rf $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin tb.out tb.vcd
-
-.SECONDARY:
-.PHONY: all prog clean sim

hdl/pins.pcf

@@ -1,10 +0,0 @@
-set_io led[0]   E4
-set_io led[1]   B2
-set_io led[2]   F5
-set_io led[3]   B1
-set_io led[4]   C1
-set_io led[5]   C2
-set_io led[6]   F4
-set_io led[7]   D2
-set_io clk      G5
-set_io n_reset  D1