reorganize and add support for multiple testbenches

This commit is contained in:
Brendan Haines 2022-08-21 11:40:12 -06:00
parent e370d6835a
commit b2b17840a1
9 changed files with 71 additions and 23 deletions

8
.vscode/extensions.json vendored Normal file
View File

@ -0,0 +1,8 @@
{
"recommendations": [
"eamodio.gitlens",
"mhutchie.git-graph",
"mshr-h.veriloghdl",
"YuTengjing.open-in-external-app"
]
}

24
.vscode/settings.json vendored Normal file
View File

@ -0,0 +1,24 @@
{
"verilog.linting.linter": "iverilog",
"verilog.linting.iverilog.arguments": "-g2012 -Wall -Y .sv -i",
"openInExternalApp.openMapper": [
{
"extensionName": "gtkw",
"apps": [
{
"title": "gtkwave",
"openCommand": "gtkwave"
},
]
},
{
"extensionName": "vcd",
"apps": [
{
"title": "gtkwave",
"openCommand": "gtkwave"
},
]
}
],
}

View File

@ -1,17 +1,23 @@
PROJ = top PROJ = top
DEVICE = hx8k DEVICE = hx8k
PACKAGE = ct256 PACKAGE = ct256
# Synthesis outputs go here. Testbench outputs go with their testbenches
BUILD_DIR = build BUILD_DIR = build
PIN_DEF = constraints/pins.pcf PIN_DEF = constraints/pins.pcf
SOURCE_V = $(wildcard hdl/*.v) # NOTE: this should work fine with .sv files too
TESTBENCH_V = $(wildcard hdl/tb/*.v) # Synthesis files
SOURCE_V = $(wildcard rtl/*.v)
# Testbench files
TB_V = $(wildcard tb/**/tb_*.v)
# Testbench resources shared by all testbenches
TB_COMMON_V = $(wildcard tb/common/*.v)
TB_VCD = $(patsubst %.sv,%.vcd,$(TB_V:.v=.vcd))
all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
$(BUILD_DIR): $(BUILD_DIR)/%.blif: rtl/%.v
mkdir -p $(BUILD_DIR) mkdir -p $(BUILD_DIR)
$(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR)
yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V) yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
# yosys -p 'synth_ice40 -top top -blif $@' $< # yosys -p 'synth_ice40 -top top -blif $@' $<
@ -24,6 +30,13 @@ $(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR)
%.rpt: %.asc %.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $< icetime -d $(DEVICE) -mtr $@ $<
# Simulation files
%.out: %.v $(SOURCE_V) $(TB_COMMON_V)
iverilog $^ -o $@
%.vcd: %.out
cd $(dir $@) && $(abspath $^)
prog: $(PROJ).bin prog: $(PROJ).bin
iceprog $< iceprog $<
@ -31,14 +44,10 @@ sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!' @echo 'Executing prog as root!!!'
sudo iceprog $< sudo iceprog $<
$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR) tb: $(TB_VCD)
iverilog $^ -o $@
sim: $(BUILD_DIR)/tb.out
cd $(BUILD_DIR) && ./tb.out
clean: clean:
rm -rf $(BUILD_DIR) rm -rf $(BUILD_DIR) $(TB_VCD) $(TB_VCD:.vcd=.out)
.SECONDARY: .SECONDARY:
.PHONY: all prog clean sim .PHONY: all prog clean tb

View File

@ -2,5 +2,10 @@
Example project using Lattice ICE40 parts and [icestorm](http://www.clifford.at/icestorm/) toolchain. Example project using Lattice ICE40 parts and [icestorm](http://www.clifford.at/icestorm/) toolchain.
On Ubuntu 18.04.5 LTS, the build dependencies can be installed with: On Ubuntu 22.04.1 LTS, the build dependencies can be installed with:
`sudo apt install iverilog yosys verilator gtkwave` `sudo apt install iverilog yosys verilator gtkwave arachne-pnr`
## Viewing waveforms
`.gtkw` files use absolute paths for locating the associated `.vcd` file. Manually edit the paths in `.gtkw` files if project was cloned to a new location.

2
tb/.gitignore vendored Normal file
View File

@ -0,0 +1,2 @@
**/*.out
**/*.vcd

View File

@ -2,10 +2,10 @@
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 07:11:25 2021 [*] Fri Jul 2 07:11:25 2021
[*] [*]
[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/build/tb.vcd" [dumpfile] "/home/brendan/Documents/projects/ice40/tb/top/tb_top.vcd"
[dumpfile_mtime] "Fri Jul 2 07:10:41 2021" [dumpfile_mtime] "Fri Jul 2 07:10:41 2021"
[dumpfile_size] 14906 [dumpfile_size] 14906
[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw" [savefile] "/home/brendan/Documents/projects/ice40/tb/top/tb_top.gtkw"
[timestart] 0 [timestart] 0
[size] 1920 1052 [size] 1920 1052
[pos] -29 -29 [pos] -29 -29
@ -15,9 +15,9 @@
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 311 [sst_vpaned_height] 311
@28 @28
tb.clk tb_top.clk
tb.reset tb_top.reset
@8023 @8023
tb.led[7:0] tb_top.led[7:0]
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0

View File

@ -3,12 +3,12 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module tb(); module tb_top();
reg clk, reset; reg clk, reset;
wire [7:0] led; wire [7:0] led;
top top( top dut(
.clk(clk), .clk(clk),
.n_reset(~reset), .n_reset(~reset),
.led(led) .led(led)
@ -17,8 +17,8 @@ top top(
always #5 clk = ~clk; always #5 clk = ~clk;
initial begin initial begin
$dumpfile("tb.vcd"); $dumpfile("tb_top.vcd");
$dumpvars(0, tb); $dumpvars(0, tb_top);
clk = 0; clk = 0;
reset = 1; reset = 1;