From b2b17840a150f8460353f152c0ed73825f2ceb19 Mon Sep 17 00:00:00 2001 From: Brendan Haines Date: Sun, 21 Aug 2022 11:40:12 -0600 Subject: [PATCH] reorganize and add support for multiple testbenches --- .vscode/extensions.json | 8 +++++++ .vscode/settings.json | 24 ++++++++++++++++++++ Makefile | 33 ++++++++++++++++++---------- README.md | 9 ++++++-- {hdl => rtl}/counter.v | 0 {hdl => rtl}/top.v | 0 tb/.gitignore | 2 ++ hdl/tb/tb.gtkw => tb/top/tb_top.gtkw | 10 ++++----- hdl/tb/tb.v => tb/top/tb_top.v | 8 +++---- 9 files changed, 71 insertions(+), 23 deletions(-) create mode 100644 .vscode/extensions.json create mode 100644 .vscode/settings.json rename {hdl => rtl}/counter.v (100%) rename {hdl => rtl}/top.v (100%) create mode 100644 tb/.gitignore rename hdl/tb/tb.gtkw => tb/top/tb_top.gtkw (70%) rename hdl/tb/tb.v => tb/top/tb_top.v (83%) diff --git a/.vscode/extensions.json b/.vscode/extensions.json new file mode 100644 index 0000000..3fa88e0 --- /dev/null +++ b/.vscode/extensions.json @@ -0,0 +1,8 @@ +{ + "recommendations": [ + "eamodio.gitlens", + "mhutchie.git-graph", + "mshr-h.veriloghdl", + "YuTengjing.open-in-external-app" + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..504bed1 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,24 @@ +{ + "verilog.linting.linter": "iverilog", + "verilog.linting.iverilog.arguments": "-g2012 -Wall -Y .sv -i", + "openInExternalApp.openMapper": [ + { + "extensionName": "gtkw", + "apps": [ + { + "title": "gtkwave", + "openCommand": "gtkwave" + }, + ] + }, + { + "extensionName": "vcd", + "apps": [ + { + "title": "gtkwave", + "openCommand": "gtkwave" + }, + ] + } + ], +} \ No newline at end of file diff --git a/Makefile b/Makefile index eba8a05..1d09541 100644 --- a/Makefile +++ b/Makefile @@ -1,17 +1,23 @@ PROJ = top DEVICE = hx8k PACKAGE = ct256 +# Synthesis outputs go here. Testbench outputs go with their testbenches BUILD_DIR = build PIN_DEF = constraints/pins.pcf -SOURCE_V = $(wildcard hdl/*.v) -TESTBENCH_V = $(wildcard hdl/tb/*.v) +# NOTE: this should work fine with .sv files too +# Synthesis files +SOURCE_V = $(wildcard rtl/*.v) +# Testbench files +TB_V = $(wildcard tb/**/tb_*.v) +# Testbench resources shared by all testbenches +TB_COMMON_V = $(wildcard tb/common/*.v) + +TB_VCD = $(patsubst %.sv,%.vcd,$(TB_V:.v=.vcd)) all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin -$(BUILD_DIR): +$(BUILD_DIR)/%.blif: rtl/%.v mkdir -p $(BUILD_DIR) - -$(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR) yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V) # yosys -p 'synth_ice40 -top top -blif $@' $< @@ -24,6 +30,13 @@ $(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR) %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< +# Simulation files +%.out: %.v $(SOURCE_V) $(TB_COMMON_V) + iverilog $^ -o $@ + +%.vcd: %.out + cd $(dir $@) && $(abspath $^) + prog: $(PROJ).bin iceprog $< @@ -31,14 +44,10 @@ sudo-prog: $(PROJ).bin @echo 'Executing prog as root!!!' sudo iceprog $< -$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR) - iverilog $^ -o $@ - -sim: $(BUILD_DIR)/tb.out - cd $(BUILD_DIR) && ./tb.out +tb: $(TB_VCD) clean: - rm -rf $(BUILD_DIR) + rm -rf $(BUILD_DIR) $(TB_VCD) $(TB_VCD:.vcd=.out) .SECONDARY: -.PHONY: all prog clean sim +.PHONY: all prog clean tb diff --git a/README.md b/README.md index 8b9829e..6e8909b 100644 --- a/README.md +++ b/README.md @@ -2,5 +2,10 @@ Example project using Lattice ICE40 parts and [icestorm](http://www.clifford.at/icestorm/) toolchain. -On Ubuntu 18.04.5 LTS, the build dependencies can be installed with: -`sudo apt install iverilog yosys verilator gtkwave` +On Ubuntu 22.04.1 LTS, the build dependencies can be installed with: +`sudo apt install iverilog yosys verilator gtkwave arachne-pnr` + + +## Viewing waveforms + +`.gtkw` files use absolute paths for locating the associated `.vcd` file. Manually edit the paths in `.gtkw` files if project was cloned to a new location. \ No newline at end of file diff --git a/hdl/counter.v b/rtl/counter.v similarity index 100% rename from hdl/counter.v rename to rtl/counter.v diff --git a/hdl/top.v b/rtl/top.v similarity index 100% rename from hdl/top.v rename to rtl/top.v diff --git a/tb/.gitignore b/tb/.gitignore new file mode 100644 index 0000000..971bbfe --- /dev/null +++ b/tb/.gitignore @@ -0,0 +1,2 @@ +**/*.out +**/*.vcd \ No newline at end of file diff --git a/hdl/tb/tb.gtkw b/tb/top/tb_top.gtkw similarity index 70% rename from hdl/tb/tb.gtkw rename to tb/top/tb_top.gtkw index 9a31377..4963867 100644 --- a/hdl/tb/tb.gtkw +++ b/tb/top/tb_top.gtkw @@ -2,10 +2,10 @@ [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI [*] Fri Jul 2 07:11:25 2021 [*] -[dumpfile] "/home/brendan/Documents/Projects/0042_ice40/build/tb.vcd" +[dumpfile] "/home/brendan/Documents/projects/ice40/tb/top/tb_top.vcd" [dumpfile_mtime] "Fri Jul 2 07:10:41 2021" [dumpfile_size] 14906 -[savefile] "/home/brendan/Documents/Projects/0042_ice40/hdl/tb/tb.gtkw" +[savefile] "/home/brendan/Documents/projects/ice40/tb/top/tb_top.gtkw" [timestart] 0 [size] 1920 1052 [pos] -29 -29 @@ -15,9 +15,9 @@ [sst_expanded] 1 [sst_vpaned_height] 311 @28 -tb.clk -tb.reset +tb_top.clk +tb_top.reset @8023 -tb.led[7:0] +tb_top.led[7:0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/hdl/tb/tb.v b/tb/top/tb_top.v similarity index 83% rename from hdl/tb/tb.v rename to tb/top/tb_top.v index 81ed4ea..ab5870c 100644 --- a/hdl/tb/tb.v +++ b/tb/top/tb_top.v @@ -3,12 +3,12 @@ `timescale 1ns/1ps -module tb(); +module tb_top(); reg clk, reset; wire [7:0] led; -top top( +top dut( .clk(clk), .n_reset(~reset), .led(led) @@ -17,8 +17,8 @@ top top( always #5 clk = ~clk; initial begin - $dumpfile("tb.vcd"); - $dumpvars(0, tb); + $dumpfile("tb_top.vcd"); + $dumpvars(0, tb_top); clk = 0; reset = 1;