reorganize and add support for multiple testbenches

rtl/counter.v

@@ -0,0 +1,17 @@
+module counter #(
+    parameter BITS = 8
+)(
+    input clk,
+    input reset,
+    output reg [BITS-1:0] y
+);
+
+always @(posedge clk or posedge reset) begin
+    if (reset) begin
+        y <= 0;
+    end else begin
+        y <= y + 1;
+    end
+end
+
+endmodule

rtl/top.v

@@ -0,0 +1,18 @@
+// Author:  Brendan Haines
+// Date:    2020-05-04
+
+module top(
+    input clk,
+    input n_reset,
+    output [7:0] led
+);
+
+counter #(
+    .BITS(8)
+) count(
+    .clk(clk),
+    .reset(~n_reset),
+    .y(led)
+);
+
+endmodule