reorganize and add support for multiple testbenches

Makefile

@@ -1,17 +1,23 @@
 PROJ = top
 DEVICE = hx8k
 PACKAGE = ct256
+# Synthesis outputs go here. Testbench outputs go with their testbenches
 BUILD_DIR = build
 PIN_DEF = constraints/pins.pcf
-SOURCE_V = $(wildcard hdl/*.v)
-TESTBENCH_V = $(wildcard hdl/tb/*.v)
+# NOTE: this should work fine with .sv files too
+# Synthesis files
+SOURCE_V = $(wildcard rtl/*.v)
+# Testbench files
+TB_V = $(wildcard tb/**/tb_*.v)
+# Testbench resources shared by all testbenches
+TB_COMMON_V = $(wildcard tb/common/*.v)
+
+TB_VCD = $(patsubst %.sv,%.vcd,$(TB_V:.v=.vcd))
 
 all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
 
-$(BUILD_DIR):
+$(BUILD_DIR)/%.blif: rtl/%.v
 	mkdir -p $(BUILD_DIR)
-
-$(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR)
 	yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
 	# yosys -p 'synth_ice40 -top top -blif $@' $<
 
@@ -24,6 +30,13 @@ $(BUILD_DIR)/%.blif: hdl/%.v | $(BUILD_DIR)
 %.rpt: %.asc
 	icetime -d $(DEVICE) -mtr $@ $<
 
+# Simulation files
+%.out: %.v $(SOURCE_V) $(TB_COMMON_V)
+	iverilog $^ -o $@
+
+%.vcd: %.out
+	cd $(dir $@) && $(abspath $^)
+
 prog: $(PROJ).bin
 	iceprog $<
 
@@ -31,14 +44,10 @@ sudo-prog: $(PROJ).bin
 	@echo 'Executing prog as root!!!'
 	sudo iceprog $<
 
-$(BUILD_DIR)/tb.out: $(SOURCE_V) $(TESTBENCH_V) | $(BUILD_DIR)
-	iverilog $^ -o $@
-
-sim: $(BUILD_DIR)/tb.out
-	cd $(BUILD_DIR) && ./tb.out
+tb: $(TB_VCD)
 
 clean:
-	rm -rf $(BUILD_DIR)
+	rm -rf $(BUILD_DIR) $(TB_VCD) $(TB_VCD:.vcd=.out)
 
 .SECONDARY:
-.PHONY: all prog clean sim
+.PHONY: all prog clean tb