ice40/Makefile

PROJ = top
DEVICE = hx8k
PACKAGE = ct256
# Synthesis outputs go here. Testbench outputs go with their testbenches
BUILD_DIR = build
PIN_DEF = constraints/pins.pcf
# NOTE: this should work fine with .sv files too
# Synthesis files
SOURCE_V = $(wildcard rtl/*.v)
# Testbench files
TB_V = $(wildcard tb/**/tb_*.v)
# Testbench resources shared by all testbenches
TB_COMMON_V = $(wildcard tb/common/*.v)

TB_VCD = $(patsubst %.sv,%.vcd,$(TB_V:.v=.vcd))

all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin

$(BUILD_DIR)/%.blif: rtl/%.v
	mkdir -p $(BUILD_DIR)
	yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
	# yosys -p 'synth_ice40 -top top -blif $@' $<

%.asc: $(PIN_DEF) %.blif
	arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -P $(PACKAGE) -o $@ -p $^

%.bin: %.asc
	icepack $< $@

%.rpt: %.asc
	icetime -d $(DEVICE) -mtr $@ $<

# Simulation files
%.out: %.v $(SOURCE_V) $(TB_COMMON_V)
	iverilog $^ -o $@

%.vcd: %.out
	cd $(dir $@) && $(abspath $^)

prog: $(PROJ).bin
	iceprog $<

sudo-prog: $(PROJ).bin
	@echo 'Executing prog as root!!!'
	sudo iceprog $<

tb: $(TB_VCD)

clean:
	rm -rf $(BUILD_DIR) $(TB_VCD) $(TB_VCD:.vcd=.out)

.SECONDARY:
.PHONY: all prog clean tb