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https://gitlab.com/brendanhaines/ice40.git
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54 lines
1.2 KiB
Makefile
54 lines
1.2 KiB
Makefile
PROJ = top
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DEVICE = hx8k
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PACKAGE = ct256
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# Synthesis outputs go here. Testbench outputs go with their testbenches
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BUILD_DIR = build
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PIN_DEF = constraints/pins.pcf
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# NOTE: this should work fine with .sv files too
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# Synthesis files
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SOURCE_V = $(wildcard rtl/*.v)
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# Testbench files
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TB_V = $(wildcard tb/**/tb_*.v)
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# Testbench resources shared by all testbenches
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TB_COMMON_V = $(wildcard tb/common/*.v)
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TB_VCD = $(patsubst %.sv,%.vcd,$(TB_V:.v=.vcd))
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all: $(BUILD_DIR)/$(PROJ).rpt $(BUILD_DIR)/$(PROJ).bin
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$(BUILD_DIR)/%.blif: rtl/%.v
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mkdir -p $(BUILD_DIR)
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yosys -p 'synth_ice40 -top top -blif $@' $(SOURCE_V)
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# yosys -p 'synth_ice40 -top top -blif $@' $<
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%.asc: $(PIN_DEF) %.blif
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arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -P $(PACKAGE) -o $@ -p $^
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%.bin: %.asc
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icepack $< $@
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%.rpt: %.asc
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icetime -d $(DEVICE) -mtr $@ $<
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# Simulation files
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%.out: %.v $(SOURCE_V) $(TB_COMMON_V)
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iverilog $^ -o $@
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%.vcd: %.out
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cd $(dir $@) && $(abspath $^)
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prog: $(PROJ).bin
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iceprog $<
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sudo-prog: $(PROJ).bin
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@echo 'Executing prog as root!!!'
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sudo iceprog $<
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tb: $(TB_VCD)
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clean:
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rm -rf $(BUILD_DIR) $(TB_VCD) $(TB_VCD:.vcd=.out)
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.SECONDARY:
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.PHONY: all prog clean tb
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