cpu/tests/common/axi4_lite_tb.sv

module axi4_lite_tb();

parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 32;

logic clk = 0;
logic reset = 1;

logic axil_awvalid;
logic axil_awready;
logic [ADDR_WIDTH-1:0] axil_awaddr;
logic [2:0] axil_awprot;

logic axil_wvalid;
logic axil_wready;
logic [DATA_WIDTH-1:0] axil_wdata;
logic [DATA_WIDTH/8 - 1:0] axil_wstrb;

logic axil_bvalid;
logic axil_bready;
logic [1:0] axil_bresp;

logic axil_arvalid;
logic axil_arready;
logic [ADDR_WIDTH-1:0] axil_araddr;
logic [2:0] axil_arprot;

logic axil_rvalid;
logic axil_rready;
logic [DATA_WIDTH-1:0] axil_rdata;
logic [2:0] axil_rresp;

logic [ADDR_WIDTH-1:0] wb_adr_o;
logic [DATA_WIDTH-1:0] wb_dat_i;
logic [DATA_WIDTH-1:0] wb_dat_o;
logic wb_we_o;
logic wb_sel_o;
logic wb_stb_o;
logic wb_ack_i;
logic wb_cyc_o;

axi4l_wb_bridge #(
    .ADDR_WIDTH(ADDR_WIDTH),
    .DATA_WIDTH(DATA_WIDTH)
) dut(
    .clk(clk),
    .reset(reset),

    ///// AXI4-Lite /////
    // Write address
    .axil_awvalid(axil_awvalid),
    .axil_awready(axil_awready),
    .axil_awaddr(axil_awaddr),
    .axil_awprot(axil_awprot),

    // Write data
    .axil_wvalid(axil_wvalid),
    .axil_wready(axil_wready),
    .axil_wdata(axil_wdata),
    .axil_wstrb(axil_wstrb),

    // Write response
    .axil_bvalid(axil_bvalid),
    .axil_bready(axil_bready),
    .axil_bresp(axil_bresp),

    // Read address
    .axil_arvalid(axil_arvalid),
    .axil_arready(axil_arready),
    .axil_araddr(axil_araddr),
    .axil_arprot(axil_arprot),

    // Read data
    .axil_rvalid(axil_rvalid),
    .axil_rready(axil_rready),
    .axil_rdata(axil_rdata),
    .axil_rresp(axil_rresp),

    ///// Wishbone /////
    .wb_adr_o(wb_adr_o),
    .wb_dat_i(wb_dat_i),
    .wb_dat_o(wb_dat_o),
    .wb_we_o(wb_we_o),
    .wb_sel_o(wb_sel_o),
    .wb_stb_o(wb_stb_o),
    .wb_ack_i(wb_ack_i),
    .wb_cyc_o(wb_cyc_o)
);

always #5 clk <= !clk;

initial begin
    
end

endmodule