Brendan Haines f12d3be0bd update makefile		2022-12-01 01:05:39 -07:00
..
common	restructure testbenches and common code	2022-12-01 00:45:57 -07:00
test_basic	update makefile	2022-12-01 01:05:39 -07:00
test_c	use systemverilog 2012 for simulation	2022-11-19 18:41:25 -07:00
.gitignore	rename testbench to tests	2021-09-09 00:58:28 -06:00
basic_test.gtkw	rename testbench to tests	2021-09-09 00:58:28 -06:00
Makefile	rename testbench to tests	2021-09-09 00:58:28 -06:00