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54 lines
1.2 KiB
Systemverilog
54 lines
1.2 KiB
Systemverilog
module skidbuffer #(
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parameter WIDTH = 1
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)(
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input logic clk,
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input logic reset,
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input logic [WIDTH-1:0] in,
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input logic in_valid,
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output logic in_ready,
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output logic [WIDTH-1:0] out,
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output logic out_valid,
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input logic out_ready
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);
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logic buffer_filled = 0;
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logic [WIDTH-1:0] buffer_val;
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always_ff @(posedge clk) begin
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if (reset) begin
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buffer_filled <= 0;
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end else begin
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if (in_valid && in_ready) begin
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// input always gets stored whether it needs to be or not
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buffer_val <= in;
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end
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if (buffer_filled) begin
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if ((out_valid && out_ready) && !(in_valid && in_ready)) begin
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// out_valid = 1 since buffer is full
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buffer_filled <= 0;
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end
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end else begin
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if ((in_valid && in_ready) && !(out_valid && out_ready)) begin
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// in_ready = 1 since buffer is empty
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buffer_filled <= 1;
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end
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end
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end
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end
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always_comb begin
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if (buffer_filled) begin
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in_ready = out_ready;
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out_valid = 1;
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out = buffer_val;
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end else begin
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in_ready = 1;
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out_valid = in_valid;
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out = in;
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end
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end
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endmodule |