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53 lines
1.7 KiB
Systemverilog
53 lines
1.7 KiB
Systemverilog
module axil_ata(
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///// AXI4-Lite Slave /////
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// Write address
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input logic axil_awvalid,
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output logic axil_awready,
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input logic [ADDR_WIDTH-1:0] axil_awaddr,
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input logic [2:0] axil_awprot,
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// Write data
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input logic axil_wvalid,
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output logic axil_wready,
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input logic [DATA_WIDTH-1:0] axil_wdata,
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input logic [DATA_WIDTH/8 - 1:0] axil_wstrb,
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// Write response
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output logic axil_bvalid,
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input logic axil_bready,
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output logic [1:0] axil_bresp,
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// Read address
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input logic axil_arvalid,
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output logic axil_arready,
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input logic [ADDR_WIDTH-1:0] axil_araddr,
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input logic [2:0] axil_arprot,
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// Read data
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output logic axil_rvalid,
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input logic axil_rready,
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output logic [DATA_WIDTH-1:0] axil_rdata,
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output logic [1:0] axil_rresp,
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///// Parallel ATA Master /////
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output logic ata_n_reset, // reset
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inout wire [15:0] ata_data, // data
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output logic ata_n_diow, // write strobe
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output logic ata_n_dior, // read strobe
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input wire ata_iordy, //
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input wire ata_irq, // interrupt request
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output logic [2:0] ata_addr, // address
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output logic [1:0] ata_n_cs, // chip select
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input wire ata_activity, // LED driver
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xx wire ata_cable_select, //
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xx wire ata_dmarq, // DMA request
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xx wire ata_ddack, // DMA acknowledge
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xx wire ata_gpio_dma66_detect, //
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xx wire ata_n_iocs16 // IO ChipSelect 16
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);
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endmodule |