module axil_ata(

    ///// AXI4-Lite Slave /////

    // Write address
    input logic axil_awvalid,
    output logic axil_awready,
    input logic [ADDR_WIDTH-1:0] axil_awaddr,
    input logic [2:0] axil_awprot,

    // Write data
    input logic axil_wvalid,
    output logic axil_wready,
    input logic [DATA_WIDTH-1:0] axil_wdata,
    input logic [DATA_WIDTH/8 - 1:0] axil_wstrb,

    // Write response
    output logic axil_bvalid,
    input logic axil_bready,
    output logic [1:0] axil_bresp,

    // Read address
    input logic axil_arvalid,
    output logic axil_arready,
    input logic [ADDR_WIDTH-1:0] axil_araddr,
    input logic [2:0] axil_arprot,

    // Read data
    output logic axil_rvalid,
    input logic axil_rready,
    output logic [DATA_WIDTH-1:0] axil_rdata,
    output logic [1:0] axil_rresp,

    ///// Parallel ATA Master /////
    output  logic           ata_n_reset,            // reset
    inout   wire    [15:0]  ata_data,               // data
    output  logic           ata_n_diow,             // write strobe
    output  logic           ata_n_dior,             // read strobe
    input   wire            ata_iordy,              //
    input   wire            ata_irq,                // interrupt request
    output  logic   [2:0]   ata_addr,               // address
    output  logic   [1:0]   ata_n_cs,               // chip select
    input   wire            ata_activity,           // LED driver
    xx      wire            ata_cable_select,       //
    xx      wire            ata_dmarq,              // DMA request
    xx      wire            ata_ddack,              // DMA acknowledge
    xx      wire            ata_gpio_dma66_detect,  //
    xx      wire            ata_n_iocs16            // IO ChipSelect 16
);



endmodule