36 lines
1.2 KiB
Markdown
36 lines
1.2 KiB
Markdown
# RISC-V CPU
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Short Term To Do:
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- [ ] add stalls for memory access
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- [ ] use AXI for memory access (depends on AXIL memory module for test)
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- [ ] add tests for non-pipelined case
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- [ ] get C working (may depend on memory stalls)
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Desired features:
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- [ ] 1- or 5-stage pipeline selectable via parameter
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- [ ] AXI-lite Master for both instruction and data memory
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- [ ] 32, 64, (or 128?) bit word size
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- [ ] floating point
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- [ ] multiplication
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- [ ] division
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- [ ] instruction and data caches
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- [ ] JTAG debug probe
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## Development
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### Testing
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I'm using [act](https://github.com/nektos/act) for local testing. No special installation is required since everything gets built and tested in containers as part of the CI actions.
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To run the tests, use
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```bash
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act push
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```
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## Resources
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* [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)
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* [JTAG Bus Description](https://web.archive.org/web/20230314233136/http://www.interfacebus.com/Design_Connector_JTAG_Bus.html)
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* [1149.1-2013 - IEEE Standard for Test Access Port and Boundary-Scan Architecture](https://ieeexplore.ieee.org/document/6515989)
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## Attribution
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* [Icon](https://www.flaticon.com/free-icon/cpu_543275) |