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comments n stuff
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@ -19,4 +19,7 @@ Desired features:
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* JTAG debug probe
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## Installation
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Run `setup.sh` to install GCC
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Run `setup.sh` to install GCC
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## Resources
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* [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)
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@ -4,7 +4,6 @@ module axi4l_wb_bridge #(
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parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 32
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)(
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// Global
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input logic clk,
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input logic reset,
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96
tests/common/axi4_lite_tb.sv
Normal file
96
tests/common/axi4_lite_tb.sv
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@ -0,0 +1,96 @@
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module axi4_lite_tb();
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parameter ADDR_WIDTH = 8;
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parameter DATA_WIDTH = 32;
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logic clk = 0;
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logic reset = 1;
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logic axil_awvalid;
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logic axil_awready;
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logic [ADDR_WIDTH-1:0] axil_awaddr;
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logic [2:0] axil_awprot;
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logic axil_wvalid;
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logic axil_wready;
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logic [DATA_WIDTH-1:0] axil_wdata;
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logic [DATA_WIDTH/8 - 1:0] axil_wstrb;
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logic axil_bvalid;
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logic axil_bready;
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logic [1:0] axil_bresp;
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logic axil_arvalid;
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logic axil_arready;
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logic [ADDR_WIDTH-1:0] axil_araddr;
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logic [2:0] axil_arprot;
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logic axil_rvalid;
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logic axil_rready;
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logic [DATA_WIDTH-1:0] axil_rdata;
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logic [2:0] axil_rresp;
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logic [ADDR_WIDTH-1:0] wb_adr_o;
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logic [DATA_WIDTH-1:0] wb_dat_i;
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logic [DATA_WIDTH-1:0] wb_dat_o;
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logic wb_we_o;
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logic wb_sel_o;
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logic wb_stb_o;
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logic wb_ack_i;
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logic wb_cyc_o;
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axi4l_wb_bridge #(
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.ADDR_WIDTH(ADDR_WIDTH),
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.DATA_WIDTH(DATA_WIDTH)
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) dut(
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.clk(clk),
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.reset(reset),
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///// AXI4-Lite /////
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// Write address
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.axil_awvalid(axil_awvalid),
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.axil_awready(axil_awready),
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.axil_awaddr(axil_awaddr),
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.axil_awprot(axil_awprot),
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// Write data
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.axil_wvalid(axil_wvalid),
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.axil_wready(axil_wready),
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.axil_wdata(axil_wdata),
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.axil_wstrb(axil_wstrb),
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// Write response
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.axil_bvalid(axil_bvalid),
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.axil_bready(axil_bready),
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.axil_bresp(axil_bresp),
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// Read address
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.axil_arvalid(axil_arvalid),
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.axil_arready(axil_arready),
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.axil_araddr(axil_araddr),
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.axil_arprot(axil_arprot),
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// Read data
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.axil_rvalid(axil_rvalid),
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.axil_rready(axil_rready),
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.axil_rdata(axil_rdata),
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.axil_rresp(axil_rresp),
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///// Wishbone /////
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.wb_adr_o(wb_adr_o),
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.wb_dat_i(wb_dat_i),
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.wb_dat_o(wb_dat_o),
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.wb_we_o(wb_we_o),
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.wb_sel_o(wb_sel_o),
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.wb_stb_o(wb_stb_o),
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.wb_ack_i(wb_ack_i),
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.wb_cyc_o(wb_cyc_o)
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);
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always #5 clk <= !clk;
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initial begin
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end
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endmodule
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