From f770ad28c776a998b7a78d2c7ec18cbfe9c29efd Mon Sep 17 00:00:00 2001
From: Brendan Haines <brendan.haines@gmail.com>
Date: Sat, 19 Nov 2022 21:24:08 -0700
Subject: [PATCH] comments n stuff

---
 README.md                    |  5 +-
 tests/common/axi4_lite.sv    |  1 -
 tests/common/axi4_lite_tb.sv | 96 ++++++++++++++++++++++++++++++++++++
 3 files changed, 100 insertions(+), 2 deletions(-)
 create mode 100644 tests/common/axi4_lite_tb.sv

diff --git a/README.md b/README.md
index 674df3b..bb2e6d0 100644
--- a/README.md
+++ b/README.md
@@ -19,4 +19,7 @@ Desired features:
 * JTAG debug probe
 
 ## Installation
-Run `setup.sh` to install GCC
\ No newline at end of file
+Run `setup.sh` to install GCC
+
+## Resources
+* [AXI4 Protocol Specification](https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification?lang=en)
diff --git a/tests/common/axi4_lite.sv b/tests/common/axi4_lite.sv
index 31c6a4d..c8230ae 100644
--- a/tests/common/axi4_lite.sv
+++ b/tests/common/axi4_lite.sv
@@ -4,7 +4,6 @@ module axi4l_wb_bridge #(
     parameter ADDR_WIDTH = 8,
     parameter DATA_WIDTH = 32
 )(
-    // Global
     input logic clk,
     input logic reset,
 
diff --git a/tests/common/axi4_lite_tb.sv b/tests/common/axi4_lite_tb.sv
new file mode 100644
index 0000000..61124ac
--- /dev/null
+++ b/tests/common/axi4_lite_tb.sv
@@ -0,0 +1,96 @@
+module axi4_lite_tb();
+
+parameter ADDR_WIDTH = 8;
+parameter DATA_WIDTH = 32;
+
+logic clk = 0;
+logic reset = 1;
+
+logic axil_awvalid;
+logic axil_awready;
+logic [ADDR_WIDTH-1:0] axil_awaddr;
+logic [2:0] axil_awprot;
+
+logic axil_wvalid;
+logic axil_wready;
+logic [DATA_WIDTH-1:0] axil_wdata;
+logic [DATA_WIDTH/8 - 1:0] axil_wstrb;
+
+logic axil_bvalid;
+logic axil_bready;
+logic [1:0] axil_bresp;
+
+logic axil_arvalid;
+logic axil_arready;
+logic [ADDR_WIDTH-1:0] axil_araddr;
+logic [2:0] axil_arprot;
+
+logic axil_rvalid;
+logic axil_rready;
+logic [DATA_WIDTH-1:0] axil_rdata;
+logic [2:0] axil_rresp;
+
+logic [ADDR_WIDTH-1:0] wb_adr_o;
+logic [DATA_WIDTH-1:0] wb_dat_i;
+logic [DATA_WIDTH-1:0] wb_dat_o;
+logic wb_we_o;
+logic wb_sel_o;
+logic wb_stb_o;
+logic wb_ack_i;
+logic wb_cyc_o;
+
+axi4l_wb_bridge #(
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .DATA_WIDTH(DATA_WIDTH)
+) dut(
+    .clk(clk),
+    .reset(reset),
+
+    ///// AXI4-Lite /////
+    // Write address
+    .axil_awvalid(axil_awvalid),
+    .axil_awready(axil_awready),
+    .axil_awaddr(axil_awaddr),
+    .axil_awprot(axil_awprot),
+
+    // Write data
+    .axil_wvalid(axil_wvalid),
+    .axil_wready(axil_wready),
+    .axil_wdata(axil_wdata),
+    .axil_wstrb(axil_wstrb),
+
+    // Write response
+    .axil_bvalid(axil_bvalid),
+    .axil_bready(axil_bready),
+    .axil_bresp(axil_bresp),
+
+    // Read address
+    .axil_arvalid(axil_arvalid),
+    .axil_arready(axil_arready),
+    .axil_araddr(axil_araddr),
+    .axil_arprot(axil_arprot),
+
+    // Read data
+    .axil_rvalid(axil_rvalid),
+    .axil_rready(axil_rready),
+    .axil_rdata(axil_rdata),
+    .axil_rresp(axil_rresp),
+
+    ///// Wishbone /////
+    .wb_adr_o(wb_adr_o),
+    .wb_dat_i(wb_dat_i),
+    .wb_dat_o(wb_dat_o),
+    .wb_we_o(wb_we_o),
+    .wb_sel_o(wb_sel_o),
+    .wb_stb_o(wb_stb_o),
+    .wb_ack_i(wb_ack_i),
+    .wb_cyc_o(wb_cyc_o)
+);
+
+always #5 clk <= !clk;
+
+initial begin
+    
+end
+
+endmodule
\ No newline at end of file