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https://gitlab.com/brendanhaines/cpu.git
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load (word only) appears to be working
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parent
4a25ca6def
commit
f0166f1954
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@ -256,9 +256,12 @@ always @(*) begin
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default: s_id_invalid = 1;
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default: s_id_invalid = 1;
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endcase
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endcase
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end
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end
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// OP_LOAD: begin
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OP_LOAD: begin
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s_id_load = 1;
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// end
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s_id_s1 = regfile[s_id_rs1];
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s_id_s2 = s_id_immed_itype;
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// TODO: finish parsing (byte vs word. For now always assume word)
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end
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OP_STORE: begin
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OP_STORE: begin
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s_id_store = 1;
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s_id_store = 1;
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s_id_s1 = regfile[s_id_rs1];
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s_id_s1 = regfile[s_id_rs1];
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@ -468,9 +468,9 @@
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<obj_property name="ObjectShortName">r_wb_rd[4:0]</obj_property>
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<obj_property name="ObjectShortName">r_wb_rd[4:0]</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="/core_tb/dut/r_wb_ra" type="logic" db_ref_id="1">
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<wvobject fp_name="/core_tb/dut/r_wb_ra" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">r_wb_ra</obj_property>
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<obj_property name="ElementShortName">r_wb_ra[31:0]</obj_property>
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<obj_property name="ObjectShortName">r_wb_ra</obj_property>
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<obj_property name="ObjectShortName">r_wb_ra[31:0]</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="/core_tb/dut/r_wb_load_data" type="array" db_ref_id="1">
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<wvobject fp_name="/core_tb/dut/r_wb_load_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">r_wb_load_data[31:0]</obj_property>
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<obj_property name="ElementShortName">r_wb_load_data[31:0]</obj_property>
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@ -482,6 +482,14 @@
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<obj_property name="ObjectShortName">r_wb_alu_out[31:0]</obj_property>
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<obj_property name="ObjectShortName">r_wb_alu_out[31:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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</wvobject>
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<wvobject fp_name="/core_tb/dut/r_wb_jump" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">r_wb_jump</obj_property>
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<obj_property name="ObjectShortName">r_wb_jump</obj_property>
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</wvobject>
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<wvobject fp_name="/core_tb/dut/r_wb_load" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">r_wb_load</obj_property>
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<obj_property name="ObjectShortName">r_wb_load</obj_property>
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</wvobject>
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<wvobject fp_name="/core_tb/dut/s_wb_data" type="array" db_ref_id="1">
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<wvobject fp_name="/core_tb/dut/s_wb_data" type="array" db_ref_id="1">
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<obj_property name="ElementShortName">s_wb_data[31:0]</obj_property>
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<obj_property name="ElementShortName">s_wb_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">s_wb_data[31:0]</obj_property>
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<obj_property name="ObjectShortName">s_wb_data[31:0]</obj_property>
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50
test/test.S
50
test/test.S
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@ -210,28 +210,34 @@ test9:
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test10:
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test10:
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addi x30, x0, 10 # x30 = 10
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addi x30, x0, 10 # x30 = 10
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# # now for some memory stuff
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# now for some memory stuff
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# # sw
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# sw
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# la x9, someint # x9 = start of .bss
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la x9, someint # x9 = start of .bss
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# lui x10, 0x12345 # x10 = 0x12345000
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lui x10, 0x12345 # x10 = 0x12345000
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# addi x10, x10, 0x678 # x10 = 0x12345678
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addi x10, x10, 0x678 # x10 = 0x12345678
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# sw x10, 0(x9) # someint = 0x12345678
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lw x11, 0(x9) # x11 = 0xfedcba98
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# # lw x11, 0(x9) # x11 = 0x12345678
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sw x10, 0(x9) # someint = 0x12345678
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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# nop
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nop
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lw x12, 0(x9) # x12 = 0x12345678
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nop
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nop
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nop
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nop
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nop
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done:
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done:
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