restructure testbenches and common code

tests/common/axi4_lite.sv

@@ -111,6 +111,7 @@ always_ff @(posedge clk) begin
             ((axil_wvalid && axil_wready) || wdata_valid) &&
             ((axil_awvalid && axil_awready) || waddr_valid) &&
             !w_complete
+            // TODO: check for wdata_legal (and combinatorial wdata_legal)
         ) begin
             if (state_wb == STATE_IDLE) begin
                 state_wb <= STATE_WRITE;

tests/common/skidbuffer.sv

@@ -1,55 +0,0 @@
-module skidbuffer #(
-    parameter WIDTH = 1
-)(
-    input logic clk,
-    input logic reset,
-
-    input logic [WIDTH-1:0] in,
-    input logic in_valid,
-    output logic in_ready,
-
-    output logic [WIDTH-1:0] out,
-    output logic out_valid,
-    input logic out_ready
-);
-
-logic buffer_filled = 0;
-logic [WIDTH-1:0] buffer_val;
-
-always_ff @(posedge clk) begin
-    if (reset) begin
-        buffer_filled <= 0;
-    end else begin
-        if (in_valid && in_ready) begin
-            // input always gets stored whether it needs to be or not
-            buffer_val <= in;
-        end
-
-        if (buffer_filled) begin
-            if (out_ready && !(in_valid && in_ready)) begin
-                // out_valid = 1 since buffer is full
-                buffer_filled <= 0;
-            end
-        end else begin
-            if (in_valid && !(out_valid && out_ready)) begin
-                // in_ready = 1 since buffer is empty
-                buffer_val = in;
-                buffer_filled <= 1;
-            end
-        end
-    end
-end
-
-always_comb begin
-    if (buffer_filled) begin
-        in_ready = out_ready;
-        out_valid = 1;
-        out = buffer_val;
-    end else begin
-        in_ready = 1;
-        out_valid = in_valid;
-        out = in;
-    end
-end
-
-endmodule

tests/test_basic/Makefile

@@ -2,7 +2,8 @@ all: verify
 
 TESTBENCH_V = $(wildcard *tb.sv)
 SOURCE_V = $(wildcard ../../src/*.v ../../src/*.sv)
-SOURCE_V += $(wildcard ../common/*.v) $(wildcard ../common/*.sv)
+SOURCE_V += $(wildcard ../../lib/*.v ../../lib/*.sv)
+SOURCE_V += $(wildcard ../common/*.v ../common/*.sv)
 LOGS = $(TESTBENCH_V:.sv=.log)
 
 SOURCE_C = $(wildcard *.c)
@@ -51,10 +52,8 @@ LDFLAGS = -melf32lriscv_ilp32
 	./$< | tee $(patsubst %.out, %.log, $<)
 
 verify: $(LOGS)
-	@echo "Checking log for \"ERROR:\"..."
-	@! grep "ERROR:" $^
-	@echo "Checking log for \"SUCCESS:\"..."
-	@grep "SUCCESS:" $^
+	@! grep -q "ERROR" $^
+	@grep -q "SUCCESS" $^
 
 clean:
 	rm -rf *.vcd *.log *.out *.hex