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make sim will now fail if test hits fail state

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Brendan Haines 2021-07-03 20:59:03 -06:00
parent d4ed4ec2bc
commit e3c52db637
4 changed files with 74 additions and 16 deletions
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3
Makefile
View File

@ -47,9 +47,10 @@ $(BUILD_DIR)/%.elf: test/%.ld $(OBJ) | $(BUILD_DIR)
riscv64-linux-gnu-objcopy --target=verilog $< $@
$(BUILD_DIR)/core_tb.vcd: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
cd $(BUILD_DIR) && ./tb.out
cd $(BUILD_DIR) && ./tb.out | tee sim_log.txt
sim: $(BUILD_DIR)/core_tb.vcd
@grep -q "SUCCESS" $(BUILD_DIR)/sim_log.txt
## General
$(BUILD_DIR):

13
hdl/tb/core_tb.gtkw
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@ -1,15 +1,15 @@
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Sun Jul 4 01:38:44 2021
[*] Sun Jul 4 02:57:58 2021
[*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Sun Jul 4 01:37:31 2021"
[dumpfile_size] 682120
[dumpfile_mtime] "Sun Jul 4 02:57:52 2021"
[dumpfile_size] 500611
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 737900
[timestart] 0
[size] 1920 1016
[pos] -1 -1
*-13.000000 774000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-19.000000 3297000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289
@ -32,11 +32,12 @@ core_tb.mem_data_rvalid
core_tb.mem_data_wdata[31:0]
@28
core_tb.mem_data_we
@29
core_tb.mem_data_wready
@22
core_tb.mem_inst_addr[31:0]
core_tb.mem_inst_data[31:0]
@23
core_tb.\mem[2048][7:0]
@200
-
-DUT

24
hdl/tb/core_tb.v
View File

@ -2,6 +2,8 @@
module core_tb();
localparam ADDR_FAILCODE = 32'h800;
initial $timeformat(-9, 2, " ns", 20);
initial begin: dump
integer i;
@ -10,6 +12,7 @@ initial begin: dump
for (i=0; i<32; i=i+1) begin
$dumpvars(0, dut.regfile[i]);
end
$dumpvars(0, mem[ADDR_FAILCODE]);
end
reg clk, reset;
@ -104,11 +107,30 @@ initial begin
#10
reset = 0;
#5000
#10000
reset = 1;
$finish;
end
always @(posedge clk) begin
#100
case ({mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]})
32'h00000000: begin
// Initial value
end
32'hffffffff: begin
// Success
$display("%0t:\tSUCCESS: TEST PASSED", $time);
$finish;
end
default: begin
$display("%0t:\tERROR: FAILCODE = 0x%h", $time, {mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]});
#200
$finish;
end
endcase
end
always #2 clk = !clk;
core dut(

46
test/test.S
View File

@ -219,7 +219,7 @@ test10:
addi x30, x0, 10 # x30 = 10
# now for some memory stuff
# sw
la x9, someint # x9 = start of .bss
la x9, someint # x9 =
lui x10, 0x12345 # x10 = 0x12345000
addi x10, x10, 0x678 # x10 = 0x12345678
nop
@ -308,15 +308,35 @@ test13_done:
done:
la x31, failcode # x30 =
addi x30, x0, 0xff # x31 = 0x000000ff
slli x30, x30, 8 # x31 = 0x0000ff00
addi x30, x30, 0xff # x31 = 0x0000ffff
slli x30, x30, 8 # x31 = 0x00ffff00
addi x30, x30, 0xff # x31 = 0x00ffffff
slli x30, x30, 8 # x31 = 0xffffff00
addi x30, x30, 0xff # x31 = 0xfffffffe
nop
nop
nop
nop
nop
sw x30, 0(x31) # failcode = 0xffffffff
nop
nop
nop
nop
nop
lui x30, 0x10101 # x30 = 0x10101000
addi x30, x30, 0x010 # x30 = 0x10101010
# set registers to known values before loop
addi x2, x0, 1 # x1 = 1
addi x3, x0, 1 # x1 = 1
addi x4, x0, 1 # x1 = 1
addi x5, x0, 1 # x1 = 1
addi x6, x0, 1 # x1 = 1
addi x2, x0, 1 # x2 = 1
addi x3, x0, 1 # x3 = 1
addi x4, x0, 1 # x4 = 1
addi x5, x0, 1 # x5 = 1
addi x6, x0, 1 # x6 = 1
# counter and infinite loop
addi x31, x0, 1 # x1 = 1
@ -337,6 +357,18 @@ loop:
nop
fail:
la x31, failcode # x31 =
nop
nop
nop
nop
nop
sw x30, 0(x31) # failcode = test number
nop
nop
nop
nop
nop
# set some registers to make it blatantly obvious an error occurred
addi x1, x0, 0x7ff # x1 = 0x1111
addi x2, x0, 0x7ff # x1 = 0x1111
@ -368,6 +400,8 @@ test_jalr:
.data
failcode:
.word 0x00000000
someint:
.word 0xfedcba98
someint16: