make sim will now fail if test hits fail state

hdl/tb/core_tb.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sun Jul  4 01:38:44 2021
+[*] Sun Jul  4 02:57:58 2021
 [*]
 [dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
-[dumpfile_mtime] "Sun Jul  4 01:37:31 2021"
-[dumpfile_size] 682120
+[dumpfile_mtime] "Sun Jul  4 02:57:52 2021"
+[dumpfile_size] 500611
 [savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
-[timestart] 737900
+[timestart] 0
 [size] 1920 1016
 [pos] -1 -1
-*-13.000000 774000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-19.000000 3297000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] core_tb.
 [treeopen] core_tb.dut.
 [sst_width] 289
@@ -32,11 +32,12 @@ core_tb.mem_data_rvalid
 core_tb.mem_data_wdata[31:0]
 @28
 core_tb.mem_data_we
-@29
 core_tb.mem_data_wready
 @22
 core_tb.mem_inst_addr[31:0]
 core_tb.mem_inst_data[31:0]
+@23
+core_tb.\mem[2048][7:0]
 @200
 -
 -DUT

hdl/tb/core_tb.v

@@ -2,6 +2,8 @@
 
 module core_tb();
 
+localparam ADDR_FAILCODE = 32'h800;
+
 initial $timeformat(-9, 2, " ns", 20);
 initial begin: dump
     integer i;
@@ -10,6 +12,7 @@ initial begin: dump
     for (i=0; i<32; i=i+1) begin
         $dumpvars(0, dut.regfile[i]);
     end
+    $dumpvars(0, mem[ADDR_FAILCODE]);
 end
 
 reg clk, reset;
@@ -104,11 +107,30 @@ initial begin
     #10
     reset = 0;
     
-    #5000
+    #10000
     reset = 1;
     $finish;
 end
 
+always @(posedge clk) begin
+    #100
+    case ({mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]})
+        32'h00000000: begin
+            // Initial value
+        end
+        32'hffffffff: begin
+            // Success
+            $display("%0t:\tSUCCESS: TEST PASSED", $time);
+            $finish;
+        end
+        default: begin
+            $display("%0t:\tERROR: FAILCODE = 0x%h", $time, {mem[ADDR_FAILCODE+3], mem[ADDR_FAILCODE+2], mem[ADDR_FAILCODE+1], mem[ADDR_FAILCODE+0]});
+            #200
+            $finish;
+        end
+    endcase
+end
+
 always #2 clk  = !clk;
 
 core dut(