make sim will now fail if test hits fail state

2021-07-03 20:59:03 -06:00
parent d4ed4ec2bc
commit e3c52db637
4 changed files with 74 additions and 16 deletions
--- a/3
+++ b/3
@@ -47,9 +47,10 @@ $(BUILD_DIR)/%.elf: test/%.ld $(OBJ) | $(BUILD_DIR)
 	riscv64-linux-gnu-objcopy --target=verilog $< $@

 $(BUILD_DIR)/core_tb.vcd: $(BUILD_DIR)/tb.out $(BUILD_DIR)/test.hex
-	cd $(BUILD_DIR) && ./tb.out
+	cd $(BUILD_DIR) && ./tb.out | tee sim_log.txt

 sim: $(BUILD_DIR)/core_tb.vcd
+	@grep -q "SUCCESS" $(BUILD_DIR)/sim_log.txt

 ## General
 $(BUILD_DIR):