brendanhaines/cpu
1
0
Fork 0
mirror of https://gitlab.com/brendanhaines/cpu.git synced 2024-09-19 20:36:00 -06:00
Code Issues Packages Projects Releases Wiki Activity

update waveform view

Browse Source
This commit is contained in:
Brendan Haines 2021-07-02 02:02:11 -06:00
parent 5c59c97797
commit e32e451e60
2 changed files with 164 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

166
hdl/tb/core_tb.gtkw
View File

@ -1,22 +1,172 @@
[*] [*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Fri Jul 2 06:48:14 2021 [*] Fri Jul 2 08:01:39 2021
[*] [*]
[dumpfile] "/home/brendan/Documents/Projects/0039_cpu/hdl/core_tb.vcd" [dumpfile] "/home/brendan/Documents/Projects/0039_cpu/build/core_tb.vcd"
[dumpfile_mtime] "Fri Jul 2 06:46:26 2021" [dumpfile_mtime] "Fri Jul 2 07:58:09 2021"
[dumpfile_size] 667859 [dumpfile_size] 681929
[savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw" [savefile] "/home/brendan/Documents/Projects/0039_cpu/hdl/tb/core_tb.gtkw"
[timestart] 0 [timestart] 0
[size] 1871 1025 [size] 1920 1052
[pos] -1900 -2 [pos] -1 -1
*0.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-20.000000 461000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] core_tb. [treeopen] core_tb.
[treeopen] core_tb.dut.
[sst_width] 289 [sst_width] 289
[signals_width] 199 [signals_width] 241
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 301 [sst_vpaned_height] 301
@200
-TB
@28 @28
core_tb.clk core_tb.clk
core_tb.reset core_tb.reset
@200
-DUT
@22
core_tb.dut.\regfile[0][31:0]
core_tb.dut.\regfile[1][31:0]
core_tb.dut.\regfile[2][31:0]
core_tb.dut.\regfile[3][31:0]
core_tb.dut.\regfile[4][31:0]
core_tb.dut.\regfile[5][31:0]
core_tb.dut.\regfile[6][31:0]
core_tb.dut.\regfile[7][31:0]
core_tb.dut.\regfile[8][31:0]
core_tb.dut.\regfile[9][31:0]
core_tb.dut.\regfile[10][31:0]
core_tb.dut.\regfile[11][31:0]
core_tb.dut.\regfile[12][31:0]
core_tb.dut.\regfile[13][31:0]
core_tb.dut.\regfile[14][31:0]
core_tb.dut.\regfile[15][31:0]
core_tb.dut.\regfile[16][31:0]
core_tb.dut.\regfile[17][31:0]
core_tb.dut.\regfile[18][31:0]
core_tb.dut.\regfile[19][31:0]
core_tb.dut.\regfile[20][31:0]
core_tb.dut.\regfile[21][31:0]
core_tb.dut.\regfile[22][31:0]
core_tb.dut.\regfile[23][31:0]
@c00022
core_tb.dut.\regfile[24][31:0]
@28
(0)core_tb.dut.\regfile[24][31:0]
(1)core_tb.dut.\regfile[24][31:0]
(2)core_tb.dut.\regfile[24][31:0]
(3)core_tb.dut.\regfile[24][31:0]
(4)core_tb.dut.\regfile[24][31:0]
(5)core_tb.dut.\regfile[24][31:0]
(6)core_tb.dut.\regfile[24][31:0]
(7)core_tb.dut.\regfile[24][31:0]
(8)core_tb.dut.\regfile[24][31:0]
(9)core_tb.dut.\regfile[24][31:0]
(10)core_tb.dut.\regfile[24][31:0]
(11)core_tb.dut.\regfile[24][31:0]
(12)core_tb.dut.\regfile[24][31:0]
(13)core_tb.dut.\regfile[24][31:0]
(14)core_tb.dut.\regfile[24][31:0]
(15)core_tb.dut.\regfile[24][31:0]
(16)core_tb.dut.\regfile[24][31:0]
(17)core_tb.dut.\regfile[24][31:0]
(18)core_tb.dut.\regfile[24][31:0]
(19)core_tb.dut.\regfile[24][31:0]
(20)core_tb.dut.\regfile[24][31:0]
(21)core_tb.dut.\regfile[24][31:0]
(22)core_tb.dut.\regfile[24][31:0]
(23)core_tb.dut.\regfile[24][31:0]
(24)core_tb.dut.\regfile[24][31:0]
(25)core_tb.dut.\regfile[24][31:0]
(26)core_tb.dut.\regfile[24][31:0]
(27)core_tb.dut.\regfile[24][31:0]
(28)core_tb.dut.\regfile[24][31:0]
(29)core_tb.dut.\regfile[24][31:0]
(30)core_tb.dut.\regfile[24][31:0]
(31)core_tb.dut.\regfile[24][31:0]
@1401200
-group_end
@22
core_tb.dut.\regfile[25][31:0]
core_tb.dut.\regfile[26][31:0]
core_tb.dut.\regfile[27][31:0]
@23
core_tb.dut.\regfile[28][31:0]
@22
core_tb.dut.\regfile[29][31:0]
core_tb.dut.\regfile[30][31:0]
core_tb.dut.\regfile[31][31:0]
@200
-
@c00022
core_tb.dut.r_if_pc[31:0]
@28
(0)core_tb.dut.r_if_pc[31:0]
(1)core_tb.dut.r_if_pc[31:0]
(2)core_tb.dut.r_if_pc[31:0]
(3)core_tb.dut.r_if_pc[31:0]
(4)core_tb.dut.r_if_pc[31:0]
(5)core_tb.dut.r_if_pc[31:0]
(6)core_tb.dut.r_if_pc[31:0]
(7)core_tb.dut.r_if_pc[31:0]
(8)core_tb.dut.r_if_pc[31:0]
(9)core_tb.dut.r_if_pc[31:0]
(10)core_tb.dut.r_if_pc[31:0]
(11)core_tb.dut.r_if_pc[31:0]
(12)core_tb.dut.r_if_pc[31:0]
(13)core_tb.dut.r_if_pc[31:0]
(14)core_tb.dut.r_if_pc[31:0]
(15)core_tb.dut.r_if_pc[31:0]
(16)core_tb.dut.r_if_pc[31:0]
(17)core_tb.dut.r_if_pc[31:0]
(18)core_tb.dut.r_if_pc[31:0]
(19)core_tb.dut.r_if_pc[31:0]
(20)core_tb.dut.r_if_pc[31:0]
(21)core_tb.dut.r_if_pc[31:0]
(22)core_tb.dut.r_if_pc[31:0]
(23)core_tb.dut.r_if_pc[31:0]
(24)core_tb.dut.r_if_pc[31:0]
(25)core_tb.dut.r_if_pc[31:0]
(26)core_tb.dut.r_if_pc[31:0]
(27)core_tb.dut.r_if_pc[31:0]
(28)core_tb.dut.r_if_pc[31:0]
(29)core_tb.dut.r_if_pc[31:0]
(30)core_tb.dut.r_if_pc[31:0]
(31)core_tb.dut.r_if_pc[31:0]
@1401200
-group_end
@200
-
@28
core_tb.dut.r_id_valid
@22
core_tb.dut.r_id_pc[31:0]
core_tb.dut.r_id_inst[31:0]
@200
-
@28
core_tb.dut.r_ex_valid
@22
core_tb.dut.r_ex_pc[31:0]
core_tb.dut.r_ex_inst[31:0]
@24
core_tb.dut.r_ex_rs1[4:0]
core_tb.dut.r_ex_rs2[4:0]
core_tb.dut.r_ex_rd[4:0]
@22
core_tb.dut.r_ex_aluop[3:0]
@28
core_tb.dut.r_ex_jump
core_tb.dut.r_ex_branch
core_tb.dut.r_ex_branch_pol
core_tb.dut.r_ex_load
core_tb.dut.r_ex_store
@200
-
@22
core_tb.dut.r_mem_pc[31:0]
@200
-
@22
core_tb.dut.r_wb_pc[31:0]
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0

8
hdl/tb/core_tb.v
View File

@ -3,9 +3,13 @@
module core_tb(); module core_tb();
initial $timeformat(-9, 2, " ns", 20); initial $timeformat(-9, 2, " ns", 20);
initial begin initial begin: dump
integer i;
$dumpfile("core_tb.vcd"); $dumpfile("core_tb.vcd");
$dumpvars(0); $dumpvars(0, core_tb);
for (i=0; i<32; i=i+1) begin
$dumpvars(0, dut.regfile[i]);
end
end end
wire dummy_out; wire dummy_out;