assert now catches X properly

lib/tb/axil_wb_bridge_tb.sv

@@ -105,6 +105,26 @@ always @(posedge clk) begin
             bh_info("Wishbone cycle active (read)");
         end
     end
+
+    if (axil_awvalid && axil_awready) begin
+        bh_info("AXIL write address cycle active");
+    end
+
+    if (axil_wvalid && axil_wready) begin
+        bh_info("AXIL write data cycle active");
+    end
+
+    if (axil_bvalid && axil_bready) begin
+        bh_info("AXIL write response cycle active");
+    end
+
+    if (axil_arvalid && axil_arready) begin
+        bh_info("AXIL read address cycle active");
+    end
+
+    if (axil_rvalid && axil_rready) begin
+        bh_info("AXIL read data cycle active");
+    end
 end
 integer i;
 
@@ -186,7 +206,7 @@ initial begin
 
     #10
     bh_assert_equal(axil_rvalid, 1, "Read rvalid");
-    bh_assert_equal(axil_rdata, 1, "Read rdata");
+    bh_assert_equal(axil_rdata, 0, "Read rdata");
     bh_assert_equal(axil_rresp, 0, "Read rresp");
     axil_rready = 1;