diff --git a/lib/bh_assert.sv b/lib/bh_assert.sv
index d780da0..d4de532 100644
--- a/lib/bh_assert.sv
+++ b/lib/bh_assert.sv
@@ -17,11 +17,11 @@ package bh_assert;
     localparam COLOR_GREEN = "\033[32m";
     localparam COLOR_NORMAL = "\033[0;39m";
 
-    task bh_assert_equal(int val, int expected, string description);
+    task bh_assert_equal(logic [127:0] val, logic [127:0] expected, string description);
         // display results
         $timeformat(-9, 2, " ns", 20);
         $display(
-            "%t: %s: %d %s %d - %s",
+            "%t: %s: %8d %s %8d - %s",
             $time,
             val === expected ? {COLOR_GREEN, "PASS", COLOR_NORMAL} : {COLOR_RED, "FAIL", COLOR_NORMAL},
             val,
diff --git a/lib/tb/axil_wb_bridge_tb.sv b/lib/tb/axil_wb_bridge_tb.sv
index 7750017..9b4b826 100644
--- a/lib/tb/axil_wb_bridge_tb.sv
+++ b/lib/tb/axil_wb_bridge_tb.sv
@@ -105,6 +105,26 @@ always @(posedge clk) begin
             bh_info("Wishbone cycle active (read)");
         end
     end
+
+    if (axil_awvalid && axil_awready) begin
+        bh_info("AXIL write address cycle active");
+    end
+
+    if (axil_wvalid && axil_wready) begin
+        bh_info("AXIL write data cycle active");
+    end
+
+    if (axil_bvalid && axil_bready) begin
+        bh_info("AXIL write response cycle active");
+    end
+
+    if (axil_arvalid && axil_arready) begin
+        bh_info("AXIL read address cycle active");
+    end
+
+    if (axil_rvalid && axil_rready) begin
+        bh_info("AXIL read data cycle active");
+    end
 end
 integer i;
 
@@ -186,7 +206,7 @@ initial begin
 
     #10
     bh_assert_equal(axil_rvalid, 1, "Read rvalid");
-    bh_assert_equal(axil_rdata, 1, "Read rdata");
+    bh_assert_equal(axil_rdata, 0, "Read rdata");
     bh_assert_equal(axil_rresp, 0, "Read rresp");
     axil_rready = 1;