passing simulation
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This commit is contained in:
2025-08-28 22:35:48 -06:00
parent b231133858
commit cfbc68221a

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@@ -16,18 +16,18 @@ jobs:
# # ./tests
# # extra_args: "--check_syntax=true"
enumerate-tests:
name: Enumerate tests
runs-on: ubuntu-latest
outputs:
matrix: ${{ steps.set-matrix.outputs.matrix }}
steps:
- uses: actions/checkout@v2
- id: set-matrix
run: echo "::set-output name=matrix::$(ls tests | grep test_* | jq -R -s -c 'split("\n")[:-1]')"
# enumerate-tests:
# name: Enumerate tests
# runs-on: ubuntu-latest
# outputs:
# matrix: ${{ steps.set-matrix.outputs.matrix }}
# steps:
# - uses: actions/checkout@v2
# - id: set-matrix
# run: echo "::set-output name=matrix::$(ls tests | grep test_* | jq -R -s -c 'split("\n")[:-1]')"
test:
needs: enumerate-tests
# needs: enumerate-tests
name: Run Test `${{ matrix.test }}`
runs-on: ubuntu-latest
strategy:
@@ -47,18 +47,21 @@ jobs:
riscv64-unknown-elf-gcc --version && \
cd tests/${{ matrix.test }} && \
make test.o && \
riscv64-unknown-elf-ld -melf32lriscv -T tb.ld test.o -o test.elf && \
riscv64-unknown-elf-objcopy --target=verilog test.elf test.hex && \
riscv64-unknown-elf-ld -melf32lriscv -T tb.ld test.o -o tb.elf && \
riscv64-unknown-elf-objcopy --target=verilog tb.elf tb.hex && \
echo "done" \
"
- name: Run Simulation
uses: docker://andrsmllr/iverilog:latest
uses: docker://brendanhaines/iverilog:latest
with:
entrypoint: bash
args: |
-c "\
# iverilog -g2012 -o test.out tb.sv ../../src/*.v -Y .sv -I ../../lib && \
./test.out | tee test.log &&\
cd tests/${{ matrix.test }} && \
iverilog -g2012 -o tb.out tb.sv ../../src/*.v -Y .sv -I ../../lib && \
./tb.out | tee tb.log &&\
grep -q "ERROR" tb.log || true &&\
grep -q "SUCCESS" tb.log &&\
echo "done"
"